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[招聘] 高端大气上档次的asic PM

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发表于 2013-11-21 16:50:59 | 显示全部楼层 |阅读模式

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高端大气上档次
-
一剑封候
-
经理职位
send resume to IC@hi-talent.net
Position:                                            asic
Manager, R&D(

高端大气上档次-一剑封候-经理职位
send resume to IC@hi-talent.net

Location:                                            shanghai, Beijing, Shenzhen,Wuhan, China

Job Purpose and Mandate:

This position of “Manager II, R&D” is a Mixed-Signal Design Manager focusing on ASIC / Digital Design and Verification. In addition to being a manager of Design and Verification Engineers, the mandate of this role is to act as a project lead and technical lead in the design of semiconductor integrated circuits in compliance with the project’s specifications and XXXXs’ design methodologies. The successful candidate will work on a variety of design and verification tasks, incorporating such tasks as, and not limited to, architecture definition, specification generation, RTL coding, behavioural coding, testbench and testcase generation, RTL simulation, synthesis, STA, gate-level simulation, formal verification, documentation, and prototype evaluation. As a Manager, the successful candidate will also be responsible for recruiting, project staffing, project and staff scheduling, performance reviews and career-path development of staff.

Duties:

·        
Will be responsible for team leadership and project leadership.

  • Perform staff recruiting, provide staff training, set and monitor staff schedules and goals, and perform annual performance reviews of staff.

·        
Generation of design specifications.

·        
Perform architecture studies for complex digital blocks.

·        
Write synthesizable RTL code for circuit portions of integrated circuits.

·        
Write behavioural models.

·        
Generate testbenches and testcases.

·        
Perform complex RTL simulations of circuits, interpret the results and optimize the code until the predetermined functionality is satisfied.

·        
Generate timing constraints for synthesizable designs.

·        
Perform logic synthesis and/or static timing analysis.

·        
Perform gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied.

·        
Perform mixed-mode simulations.

·        
Documentation of functionality, code, verification environments/plans, and design procedures.

·        
May participate in prototype evaluation using bench top laboratory instruments or automated test equipment.

·        
Communicate with other XXXXs employees regarding customer technical support.

·        
May communicate directly with customers regarding technical support.

·        
Other related duties as assigned by the manager.

Requirements:

·        
Requires a degree in Engineering or Applied Science (or equivalent) and 5+ years working experience in a related field.

·        
Familiarity with verilog circuit design and design verification.

·        
Previous staff management experience.

·        
Previous Team and/or Project Leadership experience.

·        

Best Regards,

Jane.Jin

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

上海芯相会企业管理咨询有限公司

上海芯得企业管理咨询有限公司

Skype:     
ScarlettJaneJin

E-Mail:     
Jane-Jin@Hi-Talent.net

QQ:        
983144394

Blog:      
http://blog.sina.com.cn/u/1716864892

Weibo:     
http://weibo.com/u/1716864892

webside  
www.hi-talent.cn


                               
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