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在Place & route出现的,虽是warning,但是显示布线失败。下面的信号都是用MIG生成的DDR2模块的中间信号。 请问怎么解决呢?
WARNINGarHelpers:360 - Design is not completely routed.
u_mem_ddr2/c3_sysclk_2x
u_mem_ddr2/c3_sysclk_2x_180
u_mem_ddr2/memc3_infrastructure_inst/c3_sysclk_2x_180_c
u_mem_ddr2/memc3_infrastructure_inst/c3_sysclk_2x_c
u_mem_ddr2/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
u_mem_ddr2/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/ioi_drp_clk_c
资源分配情况,几个主要的
Slice Logic Utilization Used Available Utilization Note(s)
Slice Logic Utilization Used Available Utilization Note(s)
Number of occupied Slices 1,936 2,278 84%
Number of MUXCYs used 2,140 4,556 46%
Number of bonded IOBs 75 186 40%
Number of LOCed IOBs 75 75 100%
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%
Number of BUFG/BUFGMUXs 10 16 62%
Number of DCM/DCM_CLKGENs 1 4 25%
Number of IODELAY2/IODRP2/IODRP2_MCBs 23 248 9%
Number of BUFPLL_MCBs 1 4 25%
Number of MCBs 1 2 50%
Number of PCILOGICSEs 0 2 0%
Number of PLL_ADVs 2 2 100%
Average Fanout of Non-Clock Nets 3.44 |
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