【实习】AMD 多岗位招聘实习生

RecruiterAMD

AMD上海研发中心招聘实习生，该职位有机会接触并学习AMD最新的技术.

请感兴趣的同学务必以“所应聘职位_姓名_学校_年级_专业_每周可实习天数” 为标题，

把简历以附件形式发送到Zoe.Yu@amd.com ,请在正文称述应聘理由与优势。限2015年毕业

研究生，非诚勿扰。

1、ASICDesign Intern

Responsibilities:

AMD SCBU FEINT team ownsthe obligation for delivering high performance/low po

wer solution forcustomized chip. We are looking for interns responsible for f

ollowing IC Design tasks:

1.  Automate run the IP synthesize flow, analyzethe synthesize report and pro

vide the feedback todesigner.

2.  Before RTL design complete, clean RTL codesyntax error/CDC issue using sp

ecific tools. summarizethe report and give a feedback to designer.

3.  Be involved in database and webpage maintain.

4.  Monitor formal check and low-power check ofnetlist

Job Requirements:

•        Majorin EE, CS or related, Master Degree with ASIC project experience

s.  

•        familiarwith one or more ASIC flows (logic synthesis, STA, formality

check, Design for Power )and usage of related EDA tools.

•        Familiarwith script languages(tcl, perl etc.) in unix/linux.

•        Goodwritten and spoken English.

•        Goodcommunication skills and be able to work both independently and i

n a team.

•        3days or more per week, 6 month at least

2、PhysicalDesign Intern

Job responsibilities:

•        ImplementsASIC backend design, including floorplan, placement, CTS, r

outing, parasiticextraction, STA, Power analysis, Xtalk analysis, physical ve

rification and etc.

Knowledge Requirements:

•        Majorin EE, CS or related, Master Degree with ASIC project experience

s.  

•        Basicunderstanding of CMOS VLSI IC design knowledge.

•        Basiclogic/RTL design knowledge.

•        Basicskills in Linux, PC window setup.

•        Befamiliar with programming (TCL, Perl, shell script, C).

•        Experiencedwith back-end ASIC design and integration flow knowledge i

s plus.

•        Experiencedwith common EDA tools flow, ie: ICC/Encounter/PrimeTime/Ca

libre is plus.

•        Language:Good English read/write.

•        3days or more per week, 6 month at least

3、ASICDesign Verification

1.       deep understanding on ASIC/SOC design flow

2.       Excellent knowledge of design verification methodology, suchas VMM or OVM

and UVM.

3.       Solid experiences with simulation model creation and thetestbench build

4.       Strong RTL coding with Verilog

5.       Strong SystemVerilog experiences.

6.       Strong C/C++ software development experiences

7.       Be good at scripting language, such as Perl, C shell, Ruby,and  Makefile.

This intern position isopen, and required by several departments. If you are

interested inverification domain, send your resumes to me. thank you so much!