Digital System Design with SystemVerilog(2009)

fort2121 · 发表于 2013-10-16 19:18:31

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pupukid · 发表于 2013-10-17 01:17:52

New or ?????????????????

acer1128 · 发表于 2013-11-27 10:28:20

fort2121 发表于 2013-10-16 19:18

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Thx.

dennis.zhang · 发表于 2014-3-20 08:24:51

see see

dennis.zhang · 发表于 2014-3-20 08:32:48

see see

zyd912 · 发表于 2014-4-4 10:13:27

kanakan

applegirl · 发表于 2014-4-9 08:36:03

thanks a lot,LZ

kuolifeng · 发表于 2014-4-9 13:42:32

偏重於 digital system design (logic design), 而非 systemverilog 語法.

vinhlh · 发表于 2015-8-25 00:09:00

Digital System Design with SystemVerilog

efong · 发表于 2016-6-9 17:32:23

THANK YOU

[资料] Digital System Design with SystemVerilog(2009)