【全职】AMD上海招聘ASIC verification 工程师

RecruiterAMD

Requirements:

The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design verification.  

The candidate must have:

1.
deep understanding on ASIC/SOC design flow

2.
Excellent knowledge of design verification methodology, such as VMM or OVM and UVM.

3.
Solid experiences with simulation model creation and the testbench build

4.
Strong RTL coding with Verilog

5.
Strong SystemVerilog experiences.

6.
Strong C/C++ software development experiences

7.
Be good at scripting language, such as Perl, C shell, Ruby, and  Makefile.

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas

Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.

Responsibility:

The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.