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1.源代码如下不能生成状态转移图module fsm(
clk,
reset,
A,
K1,
K2,
state
);
input clk,reset,A;
output K1,K2;
//output[1:0] state;
reg K1,K2;
reg [1:0] state;
parameter Idle = 2'b00,
Start= 2'b01,
Stop = 2'b10,
Clear= 2'b11;
always @(posedge clk)
begin
if(!reset)
begin
state<=Idle;
K2<=0;
K1<=0;
end
else
begin
case(state)
Idle:
begin
if(A)
begin
state<=Start;
K1<=0;
end
else
begin
state<=Idle;
K2<=0;
K1<=0;
end
end
Start:
begin
if(!A)
begin
state<=Stop;
end
else
begin
state<=Start;
end
end
Stop:
begin
if(A)
begin
state<=Clear;
K2<=1;
end
else
begin
state<=Stop;
K2<=0;
K1<=0;
end
end
Clear:
begin
if(!A)
begin
state<=Idle;
K2<=0;
K1<=1;
end
else
begin
state<=Clear;
K2<=0;
K1<=0;
end
end
default:
begin
state<=Idle;
K2<=0;
K1<=0;
end
endcase
end
end
endmodule
2.源代码如下能生成状态转移图
module fsm(
clk,
reset,
A,
K1,
K2
);
input clk,reset,A;
output K1,K2;
reg K1,K2;
reg [1:0] state;
parameter Idle = 2'b00,
Start= 2'b01,
Stop = 2'b10,
Clear= 2'b11;
always @(posedge clk)
begin
if(!reset)
begin
state<=Idle;
K2<=0;
K1<=0;
end
else
begin
case(state)
Idle:
begin
if(A)
begin
state<=Start;
K1<=0;
end
else
begin
state<=Idle;
K2<=0;
K1<=0;
end
end
Start:
begin
if(!A)
begin
state<=Stop;
end
else
begin
state<=Start;
end
end
Stop:
begin
if(A)
begin
state<=Clear;
K2<=1;
end
else
begin
state<=Stop;
K2<=0;
K1<=0;
end
end
Clear:
begin
if(!A)
begin
state<=Idle;
K2<=0;
K1<=1;
end
else
begin
state<=Clear;
K2<=0;
K1<=0;
end
end
default:
begin
state<=Idle;
K2<=0;
K1<=0;
end
endcase
end
end
endmodule
请问各位大神这是什么原因 |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-8-18 16:07:36
