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发表于 2013-6-27 09:25:26
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I am not sure whether it is right or not. I always feel that it is a little unfair to compare industry IP with JSSCC. In JSSCC, you can assume almost ideal supply, ideal clock, and nominal PVT. For ADC, you don't have to care about digital power, buffer power, and clock power. For PLL, you don't have to care about supply noise. Of course, larger blocks are better.
I may be wrong on this. |
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