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1. ICC tluplus文件 问题
ICC所用到的tluplus文件，由itf文件转换得到tluplus，（ grdgenxo -itf2TLUPlus -i <ITF file> -o <TLU+ file> ），然后在运行ICC时遇到下面的问题：
TLU+ based extraction:
Resistance based on max model.
Using operating temperature of 25.00 degrees.
EKL: layer poly has pitch<width+spacing, forced pitch=width+spacing
Info: raw tluplus is detected
Info: raw tluplus is detected
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal1"; Bottom Layer = "Substrate"; Top Layer = "metal2"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal2"; Bottom Layer = "Substrate"; Top Layer = "metal3"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal3"; Bottom Layer = "Substrate"; Top Layer = "metal4"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal4"; Bottom Layer = "Substrate"; Top Layer = "metal5"; Table Type = "Lateral"
EKL_VALUE: error, "/0."
EKL_VALUE: error, "/0."
This following CapTable is missing when accessing:
TLUPlus File = "/home/GSMC_A018S6D0_TRAN_MIN.tluplus"; Reference Layer = "metal5"; Bottom Layer = "Substrate"; Top Layer = "metal6"; Table Type = "Lateral"
Getting the info of via resistance from TLU+ model
can not find resistance in tluplus for polyCont; skip ...
can not find resistance in tluplus for polyCont; skip ...
lower mask id 0, upper mask id 1, via layer 25, resistivity 0.000000
can not find resistance in tluplus for via1; skip ...
can not find resistance in tluplus for via1; skip ...
lower mask id 1, upper mask id 2, via layer 41, resistivity 0.000000
can not find resistance in tluplus for via2; skip ...
can not find resistance in tluplus for via2; skip ...
lower mask id 2, upper mask id 3, via layer 42, resistivity 0.000000
can not find resistance in tluplus for via3; skip ...
lower mask id 3, upper mask id 4, via layer 43, resistivity 0.000000
lower mask id 4, upper mask id 5, via layer 44, resistivity 0.000000
lower mask id 5, upper mask id 6, via layer 45, resistivity 0.000000
EKL: max metal layer: 6
Ignoring all CONN views
Warning: No power/ground pads are specified and no virtual pads are defined. (PNA-138)
Geometry mapping took 0.18 seconds
Name of design : Decimator_Top
Number of cell instance masters in the library : 92
Number of cell instances in the design : 16741
Power Network Synthesis Begins ...
Target IR drop : 180.000 mV
Processing net VDD ...
Average power dissipation in Decimator_Top : 20.00 mW
Power supply voltage : 1.80 V
Average current in Decimator_Top : 11.11 mA
terminate called after throwing an instance of 'TLUPlus_In_Mem_Exception_struct'
The tool has just encountered a fatal error:
If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at http://solvnet.synopsys.com/EnterACall.
* For information about the latest software releases, go to the Synopsys
SolvNet Release Library at http://solvnet.synopsys.com/ReleaseLibrary.
* For information about required Operating System patches, go to
http://www.synopsys.com/support
Fatal: Internal system error, cannot recover.
Error code=6
Release = 'C-2009.06-ICC-SP5' Architecture = 'linux' Program = 'icc_shell'
Exec = '/eda/Synopsys/icc/linux/syn/bin/galaxy_icc_exec'
'278572716 278572984 -6912 7833345 290688710 290678825 290678867 290679094 228494007 228497135 228366567 228366753 228063053 228244610 227986373 249736335 248884359 249508678 249244061 249334572 249477428 249479696 249328761 249383954 248749722 248751476 215764014 168206246 164783345 262062351 280690266 280696346 280697184 262029968 262042529 262062351 280690266 280696346 280855410 280876789 280700375 280902385 262054765 157764789 157747021 158476664 158436813 158443326 158422687 158225703 157441729 157431523 134624015 161026677 134622827 134623808 7749276'
应该怎样解决？求大神指导~~~~~~~~~~~~~
--------------------------------------------------------------------------------------------------------------------------------------------------------
2. tlup_map 问题
上面的tluplus问题是否是由tlup_map造成呢？foundry提供了两个．map文件，一个是GSMC_GDSII_Layer_Mapping_Table_for_virtuoso.map，一个是GDS2Layer.map(文件附后)。于是当时tlup_map设置如下
set tlup_map "gdsLayers.map"
看论坛里面有童子说map文件可以自己写，具体怎样写呢？
附１：GDS2Layer．map文件
;Avanti!Layer GDS2Layer[:GDS2DataType]
6 6 ; Diffusion
1 1 ; N-Well
12 12 ; Poly
15 15 ; P+
14 14 ; N+
53 53 ; VTH
25 25 ; Contact
31 31 ; Metal1
131 131 ; Metal1 text
41 41 ; Mvia1
32 32 ; Metal2
132 132 ; Metal2 text
50 50 ; Cut
42 42 ; Mvia2
33 33 ; Metal3
133 133 ; Metal3 text
43 43 ; Mvia3
34 34 ; Metal4
134 134 ; Metal4 text
44 44 ; Mvia4
35 35 ; Metal5
135 135 ; Metal5 text
45 45 ; Mvia5
36 36 ; Metal6
136 136 ; Metal6 text
60 60 ; prBoundary
27 27 ; Passivation
20 20 ; ESD1
19 19 ; PLH
18 18 ; NLH
17 17 ; PLL
16 16 ; NLL
9 9 ; DG
21 21 ; SAB
;96 96 ; Rea_P1
218 168:1 ;m1b
219 168:2 ;m2b
220 168:3 ;m3b
216 168:4 ;m4b
239 168:5 ;m5b
240 168:6 ;m6b
224 168:11 ;v1b
225 168:12 ;v2b
217 168:13 ;v3b
241 168:14 ;v4b
242 168:15 ;v5b
243 168:16 ;v6b
附2：GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map 文件
# $Id: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v 1.0 2011/04/14 03:20:21 lym Exp $
# Reference Document: GDSII_Layer_Mapping_Table_for_Customer_V0.30 doc
# $Log: GSMC_GDSII_Layer_Mapping_Table_for_Virtuoso.map,v $
# Revision 1.0 2011/04/14 03:20:21 lym
# New creation
# Add VTH/BCI layer based on GSMC_A013S7G0_Virtuoso_500.map_V1.6
#
###########################################################################
NW drawing 1 0 #NWELL
NW text 1 95 #Text of NWELL
PW drawing 2 0 #PWELL
PW text 2 95 #Text of PWELL
PWBLK drawing 3 0 #PWELL Block Layer
DNW drawing 4 0 #Deep NWELL
VSTI drawing 5 0 #Very Shallow Trench
VSTI ildtnh 5 41 #ILD Trench
ACT drawing 6 0 #Active area
ACT dummy 6 10 #Dummy Act(for customer)
LVNW drawing 7 0 #Low voltage NW
LVPW drawing 8 0 #Low voltage PW
TGO drawing 9 0 #Thick oxide 1
TGO2 drawing 10 0 #Thick oxide 2
GATE drawing 12 0 #Poly gate
GATE dummy 12 10 #Dummy Gate(for customer)
GATE text 12 95 #Poly gate text layer
NPLUS drawing 14 0 #Nimp
PPLUS drawing 15 0 #Pimp
NLDD1 drawing 16 0 #NLDD implant for Device 1
PLDD1 drawing 17 0 #PLDD implant for Device 1
NLDD2 drawing 18 0 #NLDD implant for Device 2
PLDD2 drawing 19 0 #PLDD implant for Device 2
ESD drawing 20 0 #ESD implant
SAB drawing 21 0 #Non silicided area definition
VTN drawing 22 0 #NMOS VT implant
VTP drawing 23 0 #PMOS VT implant
CT drawing 25 0 #Contact
PLYMD drawing 26 0 #Polymide for passivation
PA drawing 27 0 #Passivation
PA rdumm1 27 1 #Passivation(Negative Resistor)
OPC drawing 28 0 #OPC block layer
OPC rdumm1 28 1 #OPC block layer for ACT
OPC rdumm2 28 2 #OPC block layer for GATE
OPC rdumm3 28 3 #OPC block layer for M1
EXCL drawing 29 0 #Dummy layer for DRC unchecked
FUSE drawing 30 0 #FUSE
M1 drawing 31 0 #Metal1
M1 dummy 31 10 #Dummy Metal1(for customer)
M2 drawing 32 0 #Metal2
M2 dummy 32 10 #Dummy Metal2(for customer)
M3 drawing 33 0 #Metal3
M3 dummy 33 10 #Dummy Metal3(for customer)
M4 drawing 34 0 #Metal4
M4 dummy 34 10 #Dummy Metal4(for customer)
M5 drawing 35 0 #Metal5
M5 dummy 35 10 #Dummy Metal5(for customer)
M6 drawing 36 0 #Metal6
M6 dummy 36 10 #Dummy Metal6(for customer)
M7 drawing 37 0 #Metal7
M7 dummy 37 10 #Dummy Metal7(for customer)
M8 drawing 38 0 #Metal8
M8 dummy 38 10 #Dummy Metal8(for customer)
M9 drawing 39 0 #Metal9
M9 dummy 39 10 #Dummy Metal9(for customer)
LI drawing 40 0 #Local Interconnection Line
MV1 drawing 41 0 #Via1
MV2 drawing 42 0 #Via2
MV3 drawing 43 0 #Via3
MV4 drawing 44 0 #Via4
MV5 drawing 45 0 #Via5
MV6 drawing 46 0 #Via6
MV7 drawing 47 0 #Via7
MV8 drawing 48 0 #Via8
NACD drawing 49 0 #Dummy ACT exclusion
PSUB2 drawing 50 0 #Psub2 for multipower isolation
DUM_MCT drawing 52 0 #MIM Capacitor dummy Layer for MIM identified
VTH drawing 53 0 #For ULL eflash core devices
VTC drawing 54 0 #Cell VT implant
ACTR drawing 59 0 #For STI plannarization
prBoundary drawing 60 0 #prBoundary
NFLD drawing 61 0 #N-field implant
DUM_DIO drawing 62 0 #Diode dummy layer for LVS
DUM_BJT drawing 63 0 #BJT dummy layer for LVS
DUM_BJT iptag 63 63 #IP description layer,it couldn't be modified to lose correct IP info
NGRD drawing 64 0 #N-grade implant
PGRD drawing 65 0 #P-grade implant
DUM_CAP drawing 66 0 #POLY capacitor dummy layer for LVS
NWDMY drawing 67 0 #NWELL resistor dummy layer for DRC and LVS
RNDMY drawing 68 0 #N+ Poly resistor dummy layer for LVS
RNDMY rdumm1 68 1 #NLDD implant blocking
RPDMY drawing 70 0 #P+ Poly resistor dummy layer for LVS
RPDMY rdumm1 70 1 #PLDD implant blocking
DUM_RM drawing 71 0 #Poly resistor dummy for LVS
DUM_RM rdumm1 71 1 #Metal1 resistor dummy for LVS
DUM_RM rdumm2 71 2 #Metal2 resistor dummy for LVS
DUM_RM rdumm3 71 3 #Metal3 resistor dummy for LVS
DUM_RM rdumm4 71 4 #Metal4 resistor dummy for LVS
DUM_RM rdumm5 71 5 #Metal5 resistor dummy for LVS
DUM_RM rdumm6 71 6 #Metal6 resistor dummy for LVS
DUM_RM rdumm7 71 7 #Metal7 resistor dummy for LVS
DUM_RM rdumm30 71 30 #Thin Film metal resistor marking layer for lvs
DUM_RM rt3_lvs 71 20 #3 terminal cap,res identified layer for lvs
DUM_RM rt4_lvs 71 21 #4 terminal cap,res identified layer for lvs
DUM_CM drawing 72 0 #Parasitic Metal capacitor dummy layer
L_IN_1M drawing 73 0 #Non dummy area of Metal1
L_IN_2M drawing 74 0 #Non dummy area of Metal2
L_IN_3M drawing 75 0 #Non dummy area of Metal3
L_IN_4M drawing 76 0 #Non dummy area of Metal4
L_IN_5M drawing 77 0 #Non dummy area of Metal5
L_IN_6M drawing 78 0 #Non dummy area of Metal6
RING_MCT drawing 79 0 #For dummy MIM capacitor ring use
MTT drawing 80 0 #For Thick Top metal as an inductor
CGO drawing 82 0 #Pad out layer for staggered IO
IORL drawing 83 0 #IO rule marking layer
CSRC drawing 84 0 #IO special
BN drawing 86 0 #Buried NPLUS
BTC_PECT drawing 88 0 #Butting Contact/PNP Emitter Contact
CISO drawing 89 0 #Cell isolation (for ROM process)
VTND drawing 90 0 #Vt implant for N-ch depletion layer
VTPD drawing 91 0 #Vt implant for P-ch depletion layer
DUM_ROD drawing 92 0 #Active resistor dummy layer for LVS
N1GD drawing 93 0 #Non dummy area for gate
L_IN_7M drawing 94 0 #Non dummy area of Metal7
L_IN_8M drawing 95 0 #Non dummy area of Metal8
VTNL drawing 96 0 #Vt implant layer for NMOS lower threhold voltage
VTPL drawing 97 0 #Vt implant layer for PMOS lower threhold voltage
VTNH drawing 98 0 #Vt implant layer for NMOS higher threhold voltage
VTPH drawing 99 0 #Vt implant layer for PMOS higher threhold voltage
Boundary drawing 100 0 #Chip Boundary Layer
ROMC drawing 101 0 #ROM code implant
PFLD drawing 102 0 #P-field implant
INDDMY drawing 103 0 #Dummy layer for metal inductor
MDBLK drawing 104 0 #Dummy GATE and Metal Blocking layer
HVNW drawing 105 0 #NWELL for high voltage NMOS
HVPW drawing 106 0 #NWELL for high voltage PMOS
MCT drawing 107 0 #Metal Capacitor Top Layer
FLGT drawing 108 0 #Floating gate definition
FLGT2 drawing 109 0 #Floating gate 2 definition
PLUG drawing 110 0 #Code dummy in MROM
FGCT drawing 111 0 #Connect point with floating gate
WLSP_SPACER drawing 114 0 #Word line space
MPOL drawing 115 0 #Memory poly
GSTI drawing 116 0 #Additional STI etching
ZNIP drawing 117 0 #Zener implant
HALI drawing 118 0 #Special drawing layer,for LDD implant into anti-well region
HR drawing 119 0 #High resistance resistor
HVPO_HVGO drawing 120 0 #High Voltage Poly
VTMN drawing 122 0 #2nd Medium VTN implant
VTMP drawing 123 0 #2nd Medium VTP implant
PESD drawing 124 0 #PESD implant
INAG2 drawing 125 0 #Active and poly ignore layer for LVS
BPI drawing 126 0 #PIP capacitor bottom plate implant
PCT drawing 127 0 #Poly capacitor top plate
NPI drawing 128 0 #N-type poly gate implant
INAG drawing 130 0 #Active and poly ignore layer for LVS
M1_TEXT drawing 131 0 #Metal1 text layer
M1_TEXT rdumm1 131 1 #Text layer
M2_TEXT drawing 132 0 #Metal2 text layer
M3_TEXT drawing 133 0 #Metal3 text layer
M4_TEXT drawing 134 0 #Metal4 text layer
M5_TEXT drawing 135 0 #Metal5 text layer
M6_TEXT drawing 136 0 #Metal6 text layer
M7_TEXT drawing 137 0 #Metal7 text layer
M8_TEXT drawing 138 0 #Metal8 text layer
M9_TEXT drawing 139 0 #Metal9 text layer
MVNW drawing 141 0 #Medium Voltage Nwell
MVPW drawing 142 0 #Medium Voltage Pwell
PMDMY drawing 153 0 #Identify Metal Fuse PMDMY
NLDD0 drawing 156 0 #NLDD implant for 1.8v device in Embeded Flash
MCEL_CELL drawing 158 0 #Memory Cell
PLDD0 drawing 160 0 #PLDD implant for 1.8v device in Embeded Flash
IPBoundary drawing 161 0 #For Flash IP
IPBoundary rdumm1 161 1 #Customized IP boundary 1
IPBoundary rdumm2 161 2 #Customized IP boundary 2
IPBoundary dummy 161 10 #Photonics IP boundary
IPBoundary text 161 95 #IP_TEXT,CELL_TEXT
DUM_RF drawing 162 0 #RF device marking layer
DUM_RF dumrfd 162 11 #Identify RF mod drain terminal
DUM_RF dumrfs 162 12 #Extract metal space parameter of inductor for lvs
DUM_RF dumrfw 162 13 #Extract metal width parameter of inductor for lvs
DUM_RF dumrfr 162 14 #Extract inner diameter param of inductor for lvs
DUM_RF dumrfsym 162 15 #Symmetrical inductor marking layer
DUM_RF dumrfstd 162 16 #Standard inductor marking layer
DUM_RF labass 162 31 #Label layer for assura lvs
DUM_RF labcal1 162 32 #Label layer 1 for calibre lvs
DUM_RF labcal2 162 33 #Label layer 2 for calibre lvs
DUM_RF labcal3 162 34 #Label layer 3 for calibre lvs
DUM_RF labcal4 162 35 #Label layer 4 for calibre lvs
DUM_RF labcal5 162 36 #Label layer 5 for calibre lvs
DUM_RF labcal6 162 37 #Label layer 6 for calibre lvs
DUM_RF labcal7 162 38 #Label layer 7 for calibre lvs
DUM_RF labcal8 162 39 #Label layer 8 for calibre lvs
DUM_RF xrcblk 162 40 #Dummy layer for calibre xrc extraction
DUM_VAR drawing 163 0 #Varactor device marking layer
UDEF drawing 168 0 #special specified layer by customer
HV drawing 170 0 #HV region for 32V device
HV hv24 170 24 #Marking layer for 24V device
IHVPW drawing 171 0 #Isolated HVPW
HDNW drawing 172 0 #High voltage DNW
MCB_MCT2 drawing 173 0 #Metal Capacitor Bottom layer
LMARK drawing 174 0 #for laster repairing machine alignment
CVTN drawing 175 0 #Cell VT impant for NMOS
CVTP drawing 176 0 #Cell VT impant for PMOS
LVID drawing 177 0 #For lowpower device Vt implant
NWDE drawing 178 0 #NW Drain Extension Implant
PWDE drawing 179 0 #PW Drain Extension Implant
ESDT1 drawing 180 0 #ESD covering layer for Power Pin
ESDT2 drawing 181 0 #ESD covering layer for 5V tolerant
EPOLY drawing 182 0 #Emitter Poly
BPOLY drawing 183 0 #Base Poly
NPNEW drawing 184 0 #NPN Emitter window
NPNSCI drawing 185 0 #NPN Selective collector implant
NPNCOLL drawing 186 0 #NPN Collector implant
NPN drawing 187 0 #NPN open
ZNVT drawing 188 0 #Blockage of zero implant
CGCT drawing 189 0 #Control Gate Contact
BCI drawing 190 0 #Body Contact Implant
## As the layer-number of these layers beyond the scope of user-definable in virtuoso_5141,
## So you will not see these layers definition in .tf file.
ACT_DUM drawing 206 0 #dummy ACT layer
SDL drawing 211 0 #Special Device layer(for HV process)
GATE_DUM drawing 212 0 #dummy GATE layer
M1_DUM drawing 231 0 #dummy M1
M2_DUM drawing 232 0 #dummy M2
M3_DUM drawing 233 0 #dummy M3
M4_DUM drawing 234 0 #dummy M4
M5_DUM drawing 235 0 #dummy M5
M6_DUM drawing 236 0 #dummy M6
M7_DUM drawing 237 0 #dummy M7
M8_DUM drawing 238 0 #dummy M8
M9_DUM drawing 239 0 #dummy M9
SCHCT drawing 241 0 #Schottky Contact |
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