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发表于 2007-3-19 15:35:57
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Abstract—Different electrostatic discharge (ESD) protection
schemes have been investigated to find the optimal ESD protection
design for an analog input/output (I/O) buffer in 0.18-μm
1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp
devices were used in power-rail ESD clamp circuits to compare
the protection efficiency in analog I/O applications, namely:
1) gate-driven NMOS; 2) substrate-triggered field-oxide device,
and 3) substrate-triggered NMOS with dummy gate. From the
experimental results, the pure-diode ESD protection devices and
the power-rail ESD clamp circuit with gate-driven NMOS are
the suitable designs for the analog I/O buffer in the 0.18-μm
CMOS process. Each ESD failure mechanism was inspected by
scanning electron microscopy photograph in all the analog I/O
pins. An unexpected failure mechanism was found in the analog
I/O pins with pure-diode ESD protection design under ND-mode
ESD stress. The parasitic n-p-n bipolar transistor between the
ESD clamp device and the guard ring structure was triggered to
discharge the ESD current and cause damage under ND-mode
ESD stress. |
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