Cadence SH 招聘Product Engineer & Principal/Lead PV Design Engineer

kengteng

Cadence SH 招聘Product Engineer &
Principal/Lead PV Design Engineer

Ifyou have interest, PLS send your CV to zhangyl@cadence.com

Title: ProductEngineer- PVS

Position Description:

The Product Engineering team works withCustomers and foundries, R&D, Marketing, and the Field ApplicationsEngineers to create products that address the unique and complex needs of ourcustomers. A Physical Verification Product Engineer provides in-depth technicalexpertise in writing Physical Verification rule decks (i.e. DRC, ERC, FILL andLVS) and the usage of Physical Verification tools throughout physicalimplementation and signoff verification cycles.

Responsibilities:

Develop Physical Verification rule decks (i.e.DRC, ERC, FILL and LVS)

Setup efficient flows to improve rule deckdevelopment quality and product performance.

Run expert-level benchmarks and solve complexcustomer problems.

Work with the RD, field, customers andfoundries to identify and define product requirement and enhancement

Position Requirements:         

Knowledge of developing rule decks forcommercial physical verification tools (e.g. PVS, Calibre, Hercules, Dracula,Assura, etc.) is required.

Experience in the following areas:

- DRC, includes density, antenna, etc.

- LVS, includes device extraction, parametermeasurement, connect/stamp sequences, short isolation, etc.

- Knowledge of netlist formats SPICE, CDL,Verilog, etc.

- DFM, includes yield analysis, via insertion,OPC, FILL, etc.

Experience with layout implementation tools(e.g. Virtuoso, DesignREV, ICStation, etc.) for the creation of qualificationcells is required.

Knowledge of automating test suites for thequalification of rule decks is a plus.

Programming of Tcl, Perl, and Skill are a plus

EDUCATION: BS or MS in Electrical Engineering.

Job Title:
Principal/LeadPV Design Engineer

Job description:

1.
As an Encounter product validation engineer, he/she will contribute tooverall Encounter quality/stability and usability, enable designs easier tofinish design timing closure and chip finishing.

2.
Need to run different designs from placement/cts/optimization to finalSI timing closure, need to look at those timing degradations and analysis thereason, whether placement is not good, or optimization insert unreasonablebuffers, or routing pattern is detour, etc. Also need to analysis thosemax_tran/max_cap/DRC/power issues.

3.
Need to take new designs to add into regression suite. By given libraryand RTL netlist, she/he need to create floorplan, create powerplan, go throughAPR flow to achieve DRC clean and timing closure, to get reasonablePerformance/Power/Area metric, just like taping out designs.

4.
Can explore new flows or methodology to improve timing closureefficiency, and give customer support.

Positionrequirements:

1. Ph.D or excellent MS which is familiar with APR flow.

2. Good at STA. Know about place, routing, cts,optimization and SI analysis is a plus.

3. Know about RTL synthesis

4. Good at unix scripts, cshell. Perl is a plus

5. Strong ability in analysis and solving issues, strong ability infacing difficulty and challenges. Proactive in work.

6. Good English skill, communicationskill and good team work.