Systemverilog for Design and Verification Using UVM

baddy2323

SystemVerilog for Design and Verification using UVM
From RTL to Synthesis

Azadpour, Mark A.

2013, 300p. 100 illus..


Available Formats:
Provides a practical guide to the use of SystemVerilog for both design and verification, unlike any other book currently available

• Uses the Universal Verification Methodology (UVM) to build test-benches, in a manner accessible to novices
• Covers the practical essentials needed for design, verification, synthesis and static timing analysis, which readers might otherwise have to find in several books

This book is an “A-Z” guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification.  Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC).  To complete this book’s package as a practical guide, readers are introduced to the fundamentals of static timing analysis.

Content Level » Professional/practitioner
Keywords » ASIC Design - ASIC Verification - SystemVerilog - SystemVerilog for Design - SystemVerilog for Verification - UVM - Universal Verification Methodology - VLSI Verification

baddy2323

回复 1# baddy2323


   暂时没有pdf版本

tedazsx

sigh，没书啊，
白激动了。。。

lujunfeng111

楼主怎么没有附件啊?

immonster

回复 1# baddy2323


    标题党，很可恨啊

jae1214

Thanks a lot

313008234

没pdf确实好可惜啊

onabc

Hao Shu

liangdy013

坐等啊

kuaiyu

同坐等~