关于verilog

twtw4747

`timescale 1 ns/1 ns
module t(clk,gate_clk,load,count_clr);
input clk,gate_clk;
output load,count_clr;
reg load,count_clr;
reg[5:0] ll;
/*specify
$setup(gate_clk,load,10);
$hold(gate_clk,load,10);
$setup(gate_clk,count_clr,15);
$hold(gate_clk,count_clr,5);
endspecify*/
/*initial
fork
count_clr=0;
load=0;
join*/

always@(posedge clk )
if(gate_clk)
  begin
  ll=0;
  //load=0;
  //count_clr=0;
  end
  else
    begin
    ll=ll+1;
      case(ll)
    6'b000010: load=1; count_clr=0;
     6'b000100: load=0; count_clr=1;
      6'b000110: load=0; count_clr=0;
      default: load=0; count_clr=0;
    endcase
    end
endmodule
大家看下这段代码，由于是初学者对上面的问题不是很懂，大家看看错误在哪里啊，编译老是报错！！！