回复 3# allen_tang
The following layers are not drawn, but generated from a drawn layer through data manipulation. Please refer to process information (located after the table) to select the correct generationLayer
Name | Process | Description | Algorithm | Digitized Polarity | Comments | COMP | All | Union of Ncomp and Pcomp | Ncomp OR Pcomp | Dark | | PField | Native VT NMOS | Reverse of union of CDPwelland Nwell | CDPwell OR Nwell | Dark | PField and Nwell cum CDPwell are of different polarity, therefore PField Algorithm is the same as Nwell and CDPwell even though description calls for reverse tone of CDPwell and Nwell | All others Analog & All Logic | Reverse tone of Nwell | Nwell | Dark | Same comments as PField layer above | Pplus | All | 0.30 µm oversize of Pcomp.
No oversize at Pcomp edge butted to Ncomp. Merge if space is less than 0.6µm
after generation. | ((((Pcomp@ 0.15) AND (NOT(Ncomp@ 0.15)))@ 0.15) @ 0.3) @-0.3 | Clear | |
Process Information Each process id will have the following process id attributes available inside PLM database. Please inform process owners if one of attributes described here are ‘Blank’ or no value. For Native VT NMOS process, ‘VT Options’ must have the word ‘Native VT’:
就是这个样子的了 附件是globalfoundry0.35um工艺的design rule
yiminus046minusdr002_rev_14_7feb2013.docx
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