|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Memory scaling is in jeopardy as charge storage and sensing
mechanisms become less reliable for prevalent memory tech-
nologies, such as DRAM. In contrast, phase change memory
(PCM) storage relies on scalable current and thermal mecha-
nisms. To exploit PCM's scalability as a DRAM alternative,
PCM must be architected to address relatively long laten-
cies, high energy writes, and nite endurance.
We propose, crafted from a fundamental understanding of
PCM technology parameters, area-neutral architectural en-
hancements that address these limitations and make PCM
competitive with DRAM. A baseline PCM system is 1.6x
slower and requires 2.2x more energy than a DRAM sys-
tem. Buer reorganizations reduce this delay and energy
gap to 1.2x and 1.0x, using narrow rows to mitigate write
energy and multiple rows to improve locality and write coa-
lescing. Partial writes enhance memory endurance, provid-
ing 5.6 years of lifetime. Process scaling will further reduce
PCM energy costs and improve endurance. |
|