求助电子钟进位问题

kobexiao47

我是VERILOG初学者，这是我在百度找到的电子钟原代码，不过原本只有分钟跟秒钟
我自己多写了小时，但数到23:59:59之后应该进位成00:00:00才对
不过我写出来的却是01:11:10 请教各位高手该如何修改



`timescale 1ns / 1ps
module
clock(clk,clr,minute_h,minute_l,second_h,second_l,hour_h,hour_l);

input
clk;

input
clr;

output
[3:0]
hour_h;
//小时的高位

output
[3:0]
hour_l;
//小时的低位

output
[3:0]
minute_h;
//分钟的高位

output
[3:0]
minute_l;
//分钟的低位

output
[3:0]
second_h;
//秒钟的高位

output
[3:0]
second_l;
//秒钟的低位

reg
[3:0]
hour_h;


reg
[3:0]
hour_l;

reg
[3:0]
minute_h;


reg
[3:0]
minute_l;


reg
[3:0]
second_h;


reg
[3:0]
second_l;


reg
second_l_flag;
//秒钟低位的进位旗标

reg
second_h_flag;
//秒钟高位的进位旗标

reg
minute_l_flag;
//分钟低位的进位旗标

reg
minute_h_flag;
//分钟高位的进位旗标

reg
hour_l_flag;
//小时低位的进位旗标

reg
hour_h_flag;
//小时高位的进位旗标

reg
clk1;



//2hz的时钟频率

always
@(posedge
clk
or
negedge
clr)

begin

if(!clr)

clk1
<=
1'b0;

else if(hour_h==2&&hour_l==3&&minute_h==5&&minute_l==9&&second_h==5&&second_l==9)

begin

   second_l_flag =
1'b0;

second_h_flag =
1'b0;

minute_l_flag =
1'b0;

minute_h_flag =
1'b0;

hour_l_flag =
1'b0;

hour_h_flag
=
1'b0;
            hour_h = 4'b0000;
            hour_l = 4'b0000;

minute_h = 4'b0000;

minute_l = 4'b0000;

second_h = 4'b0000;

second_l = 4'b0000;

      
end


else

clk1
<=
~clk1;


end   



//秒钟的低位

always
@(posedge
clk1
or negedge
clr)

if(!clr)

begin

second_l
<=
4'b0000;

second_l_flag
<=
1'b0;

end


else

if(second_l==4'b1000)

begin

second_l
<=
second_l
+
1'b1;

second_l_flag
<=
1'b1;

end

else

if(second_l
<
4'b1000)

begin

second_l
<=
second_l
+
1'b1;

second_l_flag
<=
1'b0;

end

else

begin

second_l
<=
4'b0000;

second_l_flag
<=
1'b0;

end

  //秒钟的高位

always
@(negedge
second_l_flag
or
negedge
clr)

if(!clr)

begin

second_h
<=
4'b0000;

second_h_flag
<=
1'b0;

end

else

if(second_h==4'b0100)

begin

second_h
<=
second_h
+
1'b1;


second_h_flag
<=
1'b1;

end

else

if(second_h
<
4'b0100)

begin

second_h
<=
second_h
+
1'b1;


second_h_flag
<=
1'b0;

end

else

begin

second_h
<=
4'b0000;

second_h_flag
<=
1'b0;

end



//分钟的低位

always
@(negedge
second_h_flag
or negedge
clr)

if(!clr)

begin

minute_l
<=
4'b0000;

minute_l_flag
<=
1'b0;

end

else

if(minute_l==4'b1000)

begin

minute_l
<=
minute_l
+
1'b1;

minute_l_flag
<=
1'b1;

end

else

if(minute_l
<
4'b1000)

begin

minute_l
<=
minute_l
+
1'b1;

minute_l_flag
<=
1'b0;

end

else

begin

minute_l
<=
4'b0000;

minute_l_flag
<=
1'b0;

end




//分钟的高位

always
@(negedge
minute_l_flag
or
negedge
clr)

if(!clr)

begin

minute_h
<=
4'b0000;

minute_h_flag
<=
1'b0;

end

else

if(minute_h==4'b0100)

begin

minute_h
<=
minute_h
+
1'b1;


minute_h_flag
<=
1'b1;

end

else

if(minute_h
<
4'b0100)

begin

minute_h
<=
minute_h
+
1'b1;


minute_h_flag
<=
1'b0;

end

else

begin

minute_h
<=
4'b0000;

minute_h_flag
<=
1'b0;

end



//小时的低位

always
@(negedge
minute_h_flag
or negedge
clr)

if(!clr)

begin

hour_l
<=
4'b0000;

hour_l_flag
<=
1'b0;

end

else

if(hour_l==4'b1000)

begin

hour_l
<=
hour_l
+
1'b1;

hour_l_flag
<=
1'b1;

end


else

if(hour_l
<
4'b1000)

begin

hour_l
<=
hour_l
+
1'b1;

hour_l_flag
<=
1'b0;

end

else

begin

hour_l
<=
4'b0000;

   hour_l_flag
<=
1'b0;

end



//小时的高位

always
@(negedge
hour_l_flag
or
negedge
clr)

if(!clr)

begin

hour_h
<=
4'b0000;

hour_h_flag
<=
1'b0;

end




else

if(hour_h==4'b0001)

begin

hour_h
<=
hour_h
+
1'b1;


hour_h_flag
<=
1'b1;



end
     

else

if(hour_h
<
4'b0001)

begin

hour_h<=
hour_h
+
1'b1;


hour_h_flag
<=
1'b0;

end

else

begin

hour_h
<=
4'b0000;

hour_h_flag
<=
1'b0;

end
  
endmodule