急求各位大神解答，万分感谢！！Error: (vsim-3170)

lirunxiang

# Compile of dis_1080i.v was successful.
# Compile of hdmi_disp.v was successful.
# Compile of new-sccb_master.v was successful.
# Compile of pll.v was successful.
# Compile of ram_wr.v was successful.
# Compile of rom.v was successful.
# Compile of sccb.v was successful.
# Compile of sccb_ctl.v was successful.
# Compile of tb.v was successful.
# 9 compiles, 0 failed with no errors.
do sim.do
# vsim -L xilinx_corelib -L xilinx_unisims -L xilinx_simprims -lib work -novopt tb glbl
# Refreshing C:\Users\maoren\Desktop\xin1\work.tb
# Loading work.tb
# Refreshing C:\Users\maoren\Desktop\xin1\work.dis_1080i
# Loading work.dis_1080i
# ** Warning: (vsim-3009) [TSCALE] - Module 'dis_1080i' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/uut
# Refreshing C:\Users\maoren\Desktop\xin1\work.pll
# Loading work.pll
# Loading xilinx_unisims.IBUFG
# Loading xilinx_unisims.MMCM_ADV
# Loading xilinx_unisims.BUFG
# Refreshing C:\Users\maoren\Desktop\xin1\work.sccb
# Loading work.sccb
# ** Warning: (vsim-3009) [TSCALE] - Module 'sccb' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/uut/u_sccb
# Refreshing C:\Users\maoren\Desktop\xin1\work.sccb_ctl
# Loading work.sccb_ctl
# ** Warning: (vsim-3009) [TSCALE] - Module 'sccb_ctl' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/uut/u_sccb/u_sccb_ctl
# Refreshing C:\Users\maoren\Desktop\xin1\work.sccb_master
# Loading work.sccb_master
# ** Warning: (vsim-3009) [TSCALE] - Module 'sccb_master' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/uut/u_sccb/u_sccb_master
# Refreshing C:\Users\maoren\Desktop\xin1\work.rom
# Loading work.rom
# Loading xilinx_corelib.BLK_MEM_GEN_V4_3
# Loading xilinx_corelib.BLK_MEM_GEN_V4_3_mem_module
# Loading xilinx_corelib.BLK_MEM_GEN_V4_3_output_stage
# Loading xilinx_corelib.BLK_MEM_GEN_V4_3_softecc_output_reg_stage
# Refreshing C:\Users\maoren\Desktop\xin1\work.ram_wr
# Loading work.ram_wr
# Refreshing C:\Users\maoren\Desktop\xin1\work.display
# Loading work.display
# ** Warning: (vsim-3009) [TSCALE] - Module 'display' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/uut/u_display
# ** Error: (vsim-3170) Could not find 'C:\Users\maoren\Desktop\xin1\work.glbl'.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./sim.do PAUSED at line 1


查看了work文件夹里面确实没有glbl文件夹。以前的工程都会自动生成。不知道为什么？？跪求解答。万分感谢

wyqkiss

全部重新编译一遍

lirunxiang

回复 2# wyqkiss


不是全都编译成功了吗？    我一般都是直接右键compile all 全部编译的

图

尝试了好多遍，也全部删了重试过。还是一样的结果。请问是什么问题？

lirunxiang

glbl文件确实是compile后出现的，以前的工程编译后都会出现。现在的工程，综合语法都检测过的，编译后确没生成glbl。不知道为什么？？实在不懂

lirunxiang

有人吗？在线等啊

leasor

do sim.do
# vsim -L xilinx_corelib -L xilinx_unisims -L xilinx_simprims -lib work -novopt tb glbl

不要光想着代码, 熟练掌握ide也是重要的.

lirunxiang

回复 6# leasor
你好，你是说变一下-novopt 那句的顺序就行吗？glbl文件是编译时产生的吧。vsim是之后。再就是改动之后还是没生成。再请教

lirunxiang

masum

hi, thnks a lot