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楼主 |
发表于 2013-5-12 20:22:58
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畫電路圖
linux => cadence composer , ADP , Dxdesigner
windows => Dxdesigner(workview) , AMS
composer 應該夠強 , 很多 畫電路圖 沒法 verilog_in
cdl_in(spice in) .. SOC 會有些 chip design
會 analog 到 mos level , digital 停在 RTL /Gate level)
composer 用過最全 . |
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