DFT DRC violations 求debug

清水一杯 · 发表于 2013-5-8 16:36:51

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写了个简单的计数器电路做DFT综合，log出现 DRC violations，还有覆盖率才66%。综合后的电路中有

  MUX2HD1X U51 ( .A(reset_n), .B(set9_i), .S0(TestEn), .Z(n58) );
  MUX2HD1X U52 ( .A(clk), .B(set7_i), .S0(TestEn), .Z(n61) );

对应脚本
set_dft_signal -view existing_dft -type ScanClock -port "set7_i" -timing {45 55} -test_mode all_dft
set_dft_signal -view existing_dft -type Reset -port "set9_i" -active_state 0 -test_mode all_dft

log的violation如下
Begin Clock violations...

Warning: Clock set7_i connects to LE clock/data inputs CK/D of DFF cnt_r_reg[0]. (C12-1)
Information: There are 3 other cells with the same violation. (TEST-171)
Warning: Clock set9_i used as data is different than capture clock set7_i for inputs CK/D of stable DFF (cnt_r_reg[0]). (C26-1)
Information: There are 3 other cells with the same violation. (TEST-171)

Clock violations completed...
-----------------------------------------------------------------

-----------------------------------------------------------------
  DRC Report

  Total violations: 8

-----------------------------------------------------------------

8 CLOCK VIOLATIONS
   4 Leading edge port captured data affected by clock violations (C12)
   4 Clock as data different from capture clock for stable cell violations (C26)

Warning: Violations occurred during test design rule checking. (TEST-124)