Design Techniques for PTV Tolerant PLLs

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Design Techniques for PTV Tolerant PLLs_OreSU_2007.pdf (795.54 KB, 下载次数: 112 )

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The continued scaling of deep-submicron CMOS technology enables low-voltage
high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixedsignal
systems. However,
uctuations due to the manufacturing process and variations
in environmental conditions, such as supply voltage and temperature, are also
signicantly increased. As a result, the performance of PLLs that are susceptible
to process, voltage, and temperature (PVT) variations are dramatically aected.
To truly benet from process scaling, PVT tolerant designs of high-performance
PLLs are essential. In this dissertation, circuit techniques that can mitigate the
impacts of PVT variations on PLL performance are presented. In the context of
ring voltage-controlled oscillator (VCO) based PLLs, an on-chip calibration technique
for reducing the supply voltage sensitivity is described. This method rejects
supply noise while avoiding the use of supply regulation, which makes it more desirable
in the design of low-voltage high-performance ring VCOs. In a wide-tuning
range LC-VCO based PLL frequency synthesizer, design techniques for maintaining
a constant loop bandwidth are presented. Having a constant loop bandwidth
that is insensitive to PVT variations helps PLL frequency synthesizers to achieve
optimum performance in all frequency bands. The proposed circuit techniques are
validated by measurement results obtained from prototype chips. The concepts
that have been presented in the context of analog PLL implementations can be
easily migrated to digital PLLs.

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Design Techniques for PVT Tolerant Phase-Locked Loops
by
Ting Wu
A DISSERTATION
submitted to
Oregon State University
in partial fulllment of
the requirements for the
degree of
Doctor of Philosophy
Presented January 4, 2007
Commencement June 2007

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