|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
VERILOG FOR SYNTHESIS
This manual is primarily intended for students designing and testing VLSI integrated circuits.
This manual consists of four main parts:
• Primer for UNIX, for persons who have not yet worked with UNIX. It provides the minimum necessary knowledge to have some orientation in the operating system and to start Verilog.
• Primer for Verilog, to start the tool and learn the simplest steps for entering the circuit description and doing the simulation.
• A short introduction to the syntax and structure of Verilog models with special emphasis on synthesizability.
• Three full examples of circuits/systems descriptions. |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2006-12-29 12:23:02
谢谢
