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本帖最后由 zgoldz 于 2013-1-17 10:54 编辑
这几天画了一个版图，结果跑LVS总是出现如下图的错误
图中的ERC错误是因为所画的有些器件的B极不是连接到GLOBAL电位的，而是连到一个器件的输出端。
验证分析的结果是calibre会把版图上的OUT1_B这条net认成OUT0_B,还有就是认不出INB这条net。
然后从上图中可以看到有20个错误，但如果我把版图左右翻转、上下翻转或者90度翻转，错误的个数会改变，变成23、26、27或者28个错误。
如果我按照下图在LVS OPTION中设定好它的电位，结果就是下下张图中显示的——错误没有了。。。
求各位大神指教这是怎么回事，还有就是这张版图能直接这样投入使用不，还是说需要改正？（试着改了几天了，就是解决不了这问题啊 ，求有懂这问题，或者遇到过并解决掉这种问题的达人帮忙啊，谢谢！）
以下附上LVS report（是跑LVS出现20个错误时的report）
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: delay_pp07.lvs.report
LAYOUT NAME: /home1/xmuser/hang1989/h2/calibre/runlvs/delay_pp07.sp ('delay_pp07')
SOURCE NAME: _source.net_ ('delay_pp07')
RULE FILE: /home1/xmuser/hang1989/h2/calibre/runlvs/_G-DF-EFLASH_EE2PROM162N-1.8V_3.3V-2P6M-HV_R-CALIBRE-LVS-0.1_P1_01.txt_
RULE FILE TITLE: 162nm Embedded Flash and Embedded E2PROM 1.8 V/3.3 V 2P6M High Voltage Reduction Process
CREATION TIME: Thu Jan 17 09:38:15 2013
CURRENT DIRECTORY: /home1/xmuser/hang1989/h2/calibre/runlvs
USER NAME: hang1989
CALIBRE VERSION: v2008.1_32.21 Tue Apr 1 22:33:09 PDT 2008
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances.
Error: Connectivity errors.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT delay_pp07 delay_pp07
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "?VCC?" "?VDD?" "?VCC??" "VCC:?"
LVS GROUND NAME "?GND?" "?VSS?" "?GND??"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC NO
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE C(NCAP_18_G2_EF_UCFN) PARALLEL NO
LVS REDUCTION PRIORITY PARALLEL
// Trace Property
TRACE PROPERTY mn(n_18_g2_ef_ucfn) l l 3
TRACE PROPERTY mn(n_18_g2_ef_ucfn) w w 3
TRACE PROPERTY mp(p_18_g2_ef_ucfn) l l 3
TRACE PROPERTY mp(p_18_g2_ef_ucfn) w w 3
TRACE PROPERTY mn(n_33_g2_ef_ucfn) l l 3
TRACE PROPERTY mn(n_33_g2_ef_ucfn) w w 3
TRACE PROPERTY mp(p_33_g2_ef_ucfn) l l 3
TRACE PROPERTY mp(p_33_g2_ef_ucfn) w w 3
TRACE PROPERTY mn(n_pg32_g2) l l 3
TRACE PROPERTY mn(n_pg32_g2) w w 3
TRACE PROPERTY mn(n_pd32_g2) l l 3
TRACE PROPERTY mn(n_pd32_g2) w w 3
TRACE PROPERTY mp(p_l32_g2) l l 3
TRACE PROPERTY mp(p_l32_g2) w w 3
TRACE PROPERTY mp(p_l45_g2) l l 3
TRACE PROPERTY mp(p_l45_g2) w w 3
TRACE PROPERTY mn(n_pg45_g2) l l 3
TRACE PROPERTY mn(n_pg45_g2) w w 3
TRACE PROPERTY mn(n_pd45_g2) l l 3
TRACE PROPERTY mn(n_pd45_g2) w w 3
TRACE PROPERTY mp(p_l83_g2) l l 3
TRACE PROPERTY mp(p_l83_g2) w w 3
TRACE PROPERTY mn(n_pg83_g2) l l 3
TRACE PROPERTY mn(n_pg83_g2) w w 3
TRACE PROPERTY mn(n_pd83_g2) l l 3
TRACE PROPERTY mn(n_pd83_g2) w w 3
TRACE PROPERTY mn(n_nvt_18_ef_ucfn) l l 3
TRACE PROPERTY mn(n_nvt_18_ef_ucfn) w w 3
TRACE PROPERTY mn(n_hvbpw_25p_ef_ucfn) l l 3
TRACE PROPERTY mn(n_hvbpw_25p_ef_ucfn) w w 3
TRACE PROPERTY mp(p_hvdnw_25p_ef_ucfn) l l 3
TRACE PROPERTY mp(p_hvdnw_25p_ef_ucfn) w w 3
TRACE PROPERTY mp(p_mvbpw_25p_ef_ucfn) l l 3
TRACE PROPERTY mp(p_mvbpw_25p_ef_ucfn) w w 3
TRACE PROPERTY mn(n_mvbpw_25p_ef_ucfn) l l 3
TRACE PROPERTY mn(n_mvbpw_25p_ef_ucfn) w w 3
TRACE PROPERTY mn(n_mv_25p_ef_ucfn) l l 3
TRACE PROPERTY mn(n_mv_25p_ef_ucfn) w w 3
TRACE PROPERTY mn(n_ssgbpw_ef_ucfn) l l 3
TRACE PROPERTY mn(n_ssgbpw_ef_ucfn) w w 3
TRACE PROPERTY r(rspd_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rsnd_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rsnpo_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rsppo_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rnpd_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rnnd_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rnnpo_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rnppo_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rnhr_g2_ef_ucfn) l l 3
TRACE PROPERTY r(rnhr_g2_ef_ucfn) w w 3
TRACE PROPERTY r(rsnwell_w200_g2_ef_ucfn) r r 3
TRACE PROPERTY r(rsnwell_w200_ef_ucfn) r r 3
TRACE PROPERTY r(rsdnw_eflash) r r 3
TRACE PROPERTY r(rspwell_eflash) r r 3
TRACE PROPERTY r(rsnd_ef_ucfn) r r 3
TRACE PROPERTY r(rspd_ef_ucfn) r r 3
TRACE PROPERTY r(rsnpo_ef_ucfn) r r 3
TRACE PROPERTY r(rsppo_ef_ucfn) r r 3
TRACE PROPERTY r(rnnd_ef_ucfn) r r 3
TRACE PROPERTY r(rnpd_ef_ucfn) r r 3
TRACE PROPERTY r(rnnpo_ef_ucfn) r r 3
TRACE PROPERTY r(rnppo_ef_ucfn) r r 3
TRACE PROPERTY r(rnnpo_fg_eflash) r r 3
TRACE PROPERTY d(dion_g2_ef_ucfn) a a 3
TRACE PROPERTY d(dion_g2_ef_ucfn) p p 3
TRACE PROPERTY d(diop_g2_ef_ucfn) a a 3
TRACE PROPERTY d(diop_g2_ef_ucfn) p p 3
TRACE PROPERTY d(dionw_g2_ef_ucfn) a a 3
TRACE PROPERTY d(dionw_g2_ef_ucfn) p p 3
TRACE PROPERTY d(dionhpw_mvn_ef_ucfn) a a 3
TRACE PROPERTY d(dionhpw_mvn_ef_ucfn) p p 3
TRACE PROPERTY d(dionhpw_mvtn_ef_ucfn) a a 3
TRACE PROPERTY d(dionhpw_mvtn_ef_ucfn) p p 3
TRACE PROPERTY d(dionhpw_hvn_ef_ucfn) a a 3
TRACE PROPERTY d(dionhpw_hvn_ef_ucfn) p p 3
TRACE PROPERTY d(diopdn_mvp_ef_ucfn) a a 3
TRACE PROPERTY d(diopdn_mvp_ef_ucfn) p p 3
TRACE PROPERTY d(diopdn_hvp_ef_ucfn) a a 3
TRACE PROPERTY d(diopdn_hvp_ef_ucfn) p p 3
TRACE PROPERTY d(diohpwdn_mv_ef_ucfn) a a 3
TRACE PROPERTY d(diohpwdn_mv_ef_ucfn) p p 3
TRACE PROPERTY d(diohpwdn_hv_ef_ucfn) a a 3
TRACE PROPERTY d(diohpwdn_hv_ef_ucfn) p p 3
TRACE PROPERTY d(diodnw_mv_ef_ucfn) a a 3
TRACE PROPERTY d(diodnw_mv_ef_ucfn) p p 3
TRACE PROPERTY d(diodnw_hv_ef_ucfn) a a 3
TRACE PROPERTY d(diodnw_hv_ef_ucfn) p p 3
TRACE PROPERTY c(mimcaps_g2_ef_ucfn) c c 3
TRACE PROPERTY c(onocaps_g2_ef_ucfn) c c 3
TRACE PROPERTY q(pnp_v50x50_g2_ef_ucfn) a a 3
TRACE PROPERTY q(pnp_v100x100_g2_ef_ucfn) a a 3
TRACE PROPERTY q(npn_v50x50_ef_ucfn) a a 3
TRACE PROPERTY q(npn_v100x100_ef_ucfn) a a 3
TRACE PROPERTY c(ncap_18_g2_ef_ucfn) nf nf 0
TRACE PROPERTY c(ncap_18_g2_ef_ucfn) lf lf 3
TRACE PROPERTY c(ncap_18_g2_ef_ucfn) wf wf 3
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances (see below).
Error: Connectivity errors.
LAYOUT CELL NAME: delay_pp07
SOURCE CELL NAME: delay_pp07
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 8 *
Nets: 29 24 *
Instances: 51 16 * MN (4 pins)
57 15 * MP (4 pins)
16 16 C (2 pins)
8 2 * R (3 pins)
------ ------
Total Inst: 132 49
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 7
Nets: 19 19
Instances: 11 7 * MN (4 pins)
10 6 * MP (4 pins)
2 2 C (2 pins)
2 2 R (3 pins)
1 5 * INV (2 pins)
2 2 SDW2 (3 pins)
0 2 * SUP2 (3 pins)
2 0 * SMP2 (4 pins)
------ ------
Total Inst: 30 26
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 4 OUT1_B
-------------------------- --------------------------
(SMP2) utput ** missing connection **
M27(20.688,21.351):s
(SMP2):input ** missing connection **
M8(4.320,20.550):g
M62(18.610,7.982):s ** missing connection **
** missing connection ** (SUP2)utput
MM6:d
** missing connection ** (SUP2):input
MM4:g
** missing connection ** MM0:d
(SDW2):input ** unmatched connection **
M58(4.320,9.015):g
(SDW2)utput ** unmatched connection **
M57(4.320,4.242):d
** unmatched connection ** (SDW2):output
MM2:d
** unmatched connection ** (SDW2):input
MM7:g
--------------------------------------------------------------------------------------------------------------
2 Net 3 OUT0_B
-------------------------- --------------------------
(SMP2):input ** missing connection **
M9(4.320,22.791):g
(SMP2):output ** missing connection **
M26(20.688,19.110):d
M61(18.610,4.242):d ** missing connection **
** missing connection ** (SUP2):input
MM5:g
** missing connection ** (SUP2):output
MM3:d
** missing connection ** MM9:d
(SDW2):output ** unmatched connection **
M58(4.320,9.015):s
(SDW2):input ** unmatched connection **
M57(4.320,4.242):g
** unmatched connection ** (SDW2):input
MM2:g
** unmatched connection ** (SDW2):output
MM7:d
--------------------------------------------------------------------------------------------------------------
3 Net 15 ** no similar net **
--------------------------------------------------------------------------------------------------------------
4 ** no similar net ** INB
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
5 M42(40.660,12.774) MP(P_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
6 M43(40.660,19.014) MP(P_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
7 M49(46.424,17.496) MP(P_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
8 M50(46.424,21.236) MP(P_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
9 M65(25.094,1.881) MN(N_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
10 M66(25.094,8.121) MN(N_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
11 M76(47.144,1.862) MN(N_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
12 M77(47.144,5.602) MN(N_33_G2_EF_UCFN) ** missing instance **
--------------------------------------------------------------------------------------------------------------
13 (SMP2) ** missing gate **
Transistors:
M26(20.688,19.110) MP(P_33_G2_EF_UCFN)
M8(4.320,20.550) MP(P_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
14 (SMP2) ** missing gate **
Transistors:
M27(20.688,21.351) MP(P_33_G2_EF_UCFN)
M9(4.320,22.791) MP(P_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
15 ** missing gate ** (SUP2)
Transistors:
MM4 MP(P_33_G2_EF_UCFN)
MM3 MP(P_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
16 ** missing gate ** (SUP2)
Transistors:
MM5 MP(P_33_G2_EF_UCFN)
MM6 MP(P_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
17 ** missing gate ** (INV)
Transistors:
MI364 MP(P_33_G2_EF_UCFN)
MI362 MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
18 ** missing gate ** (INV)
Transistors:
MI363 MP(P_33_G2_EF_UCFN)
MI361 MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
19 ** missing gate ** (INV)
Transistors:
MI353 MP(P_33_G2_EF_UCFN)
MI352 MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
20 ** missing gate ** (INV)
Transistors:
MI5 MP(P_33_G2_EF_UCFN)
MI7 MN(N_33_G2_EF_UCFN)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 7 7 0 0
Nets: 18 18 1 1
Instances: 7 7 4 0 MN(N_33_G2_EF_UCFN)
6 6 4 0 MP(P_33_G2_EF_UCFN)
2 2 0 0 C(MIMCAPS_G2_EF_UCFN)
2 2 0 0 R(RNHR_G2_EF_UCFN)
1 1 0 4 INV
0 0 2 2 SDW2
0 0 0 2 SUP2
0 0 2 0 SMP2
------- ------- --------- ---------
Total Inst: 18 18 12 8
o Statistics:
1 passthrough source net was deleted.
102 layout mos transistors were reduced to 25.
77 mos transistors were deleted by parallel reduction.
16 parallel layout capacitors were reduced to 2.
16 parallel source capacitors were reduced to 2.
8 series layout resistors were reduced to 2. 6 connecting nets were deleted.
o Initial Correspondence Points:
Ports: VDD_PAD VSS_PAD VPP PROGRAM IN OUT OUTB
**************************************************************************************************************
DETAILED INSTANCE CONNECTIONS
LAYOUT NAME SOURCE NAME
**************************************************************************************************************
(This section contains detailed information about connections of
matched instances that are involved in net discrepancies).
--------------------------------------------------------------------------------------------------------------
M61(18.610,4.242) MN(N_33_G2_EF_UCFN) MM0 MN(N_33_G2_EF_UCFN)
s: 6 s: IB1
b: VSS_PAD b: VSS_PAD
g: 15 ** no similar net **
d: 3 ** OUT0_B **
** no similar net ** g: INB
** 4 ** d: OUT1_B
--------------------------------------------------------------------------------------------------------------
M62(18.610,7.982) MN(N_33_G2_EF_UCFN) MM9 MN(N_33_G2_EF_UCFN)
g: 16 g: INBB
d: 7 s: IB2
b: VSS_PAD b: VSS_PAD
s: 4 ** OUT1_B **
** 3 ** d: OUT0_B
**************************************************************************************************************
UNMATCHED OBJECTS
LAYOUT SOURCE
**************************************************************************************************************
(SDW2) ** unmatched gate **
Transistors:
M73(41.380,5.543) MN(N_33_G2_EF_UCFN)
M57(4.320,4.242) MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
(SDW2) ** unmatched gate **
Transistors:
M72(41.380,2.802) MN(N_33_G2_EF_UCFN)
M58(4.320,9.015) MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
** unmatched gate ** (SDW2)
Transistors:
MM8 MN(N_33_G2_EF_UCFN)
MM7 MN(N_33_G2_EF_UCFN)
--------------------------------------------------------------------------------------------------------------
** unmatched gate ** (SDW2)
Transistors:
MM1 MN(N_33_G2_EF_UCFN)
MM2 MN(N_33_G2_EF_UCFN)
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec |
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发表于 2013-1-17 10:34:06
发表于 2013-1-17 23:00:56
