8-stage Deep-pipelined MIPS CPU(文档、rtl、testbench)

xileito · 发表于 2013-1-16 20:29:16

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本帖最后由 xileito 于 2013-1-16 20:31 编辑

目录
0.  Abstract
1.  Division of Labor
2.  Detailed Strategy
2.1 Detailed Strategy
2.2 Stage Summary
2.3 Stage Details
2.4 Forwarding Paths
3.  Testing
3.1 General testing.
3.2 Victim Cache test.
3.3 Branch Predictor.
3.4 Signed/Unsigned  Multiply/Divide.
4.  Results
5.  Conclusion
6.  Appendix I (Notebooks)
7.  Appendix II (Schematics)
8.  Appendix III (Verilog Files)
9.  Appendiex IV (Testing)
10. Appendiex V (Timing)

8-state Deep-pipelined MIPS CPU.pdf (410.57 KB, 下载次数: 400 )

8-state Deep-pipelined MIPS CPU.zip (1.09 MB, 下载次数: 429 )

ID2007 · 发表于 2013-1-16 21:44:38

Xilinx FPGA版的

peepeekid · 发表于 2013-1-17 02:30:22

Take a look !

peepeekid · 发表于 2013-1-17 02:39:05

xileito,

It's OK to post other people's final project.

But, you should NOT take off the authors pages.

chengweiquan · 发表于 2013-1-17 15:42:19

8-stage Deep-pipelined MIPS CPU

xileito · 发表于 2013-1-17 20:15:16

回复 4# peepeekid

sorry for this, i got these file from my friend and these files don't have the things you mentioned..

caoluniu · 发表于 2013-1-18 13:27:43

Take a look !

baicaitop · 发表于 2013-2-8 05:55:22

So cool to have it. Thanks.

sunjimmy · 发表于 2013-2-13 08:51:11

感謝分享

qappend · 发表于 2013-4-15 10:52:27

good job ~~~

[原创] 8-stage Deep-pipelined MIPS CPU(文档、rtl、testbench)

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