130nm ESD Protection Design with Embedded SCR Structure(2005)

semico_ljj · 发表于 2006-12-29 10:23:45

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ESD Protection Design for I/O Cells With Embedded
SCR Structure as Power-Rail ESD Clamp Device
in Nanoscale CMOS Technology

Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE

Abstract
This paper presents a new electrostatic discharge
(ESD) protection design for input/output (I/O) cells with embedded
silicon-controlled rectifier (SCR) structure as power-rail
ESD clamp device in a 130-nm CMOS process. Two new embedded
SCR structures without latchup danger are proposed to be placed
between the input (or output) pMOS and nMOS devices of the
I/O cells. Furthermore, the turn-on efficiency of embedded SCR
can be significantly increased by substrate-triggered technique.
Experimental results have verified that the human-body-model
(HBM) ESD level of this new proposed I/O cells can be greater
than 5 kV in a 130-nm fully salicided CMOS process. By including
the efficient power-rail ESD clamp device into each I/O cell,
whole-chip ESD protection scheme can be successfully achieved
within a small silicon area of the I/O cell.

semico_ljj · 发表于 2006-12-29 10:25:19

REFERENCES
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semico_ljj · 发表于 2006-12-29 10:27:04

Index Terms

Electrostatic discharge (ESD), input/output (I/O)
cell, silicon controlled rectifier (SCR), power-rail ESD clamp device.

Ming-Dou Ker (S’92–M’94–SM’97)