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发表于 2013-2-28 22:40:44
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I have no experience on the dual-port SRAM. Below is my comments, more discussion is welcome.
I do not think adjusting clock edge works.
Read takes more time than write SRAM. the operation clock frequence is limited by read time.
My understanding is the SRAM user does not need to adjust the write clk and read clk
For read first, SRAM shall latch write data in register, performs read operation to get the old value, then write the latching data to the SRAM cell.
For write first, SRAM can pass write data to dout directly, meanwhile the write data is written into hte SRAM cell.
So, I think the key is that the write data is latched in the internal registers. |
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