CTS 中的各种pin

liyong_ic

Nonstop pins are pins that would normally be considered endpoints ofthe clock tree, but
instead IC Compiler traces through them to find the clock tree endpoints. Theclock pins of
sequential cells driving generated clocks are implicit nonstop pins. In addition,IC Compiler
supports user-defined (or explicit) nonstop pins.

To specify a nonstop pin, use the set_clock_tree_exceptions -non_stop_pins


Exclude pins are clock tree endpoints that are excluded from clock treetiming calculations
and optimizations. IC Compiler uses exclude pins only in calculations andoptimizations for
design rule constraints. In addition to the exclude pins inferred by ICCompiler (the implicit
exclude pins), IC Compiler supports user-defined (or explicit) exclude pins.For example, you
might define an exclude pin to exclude all branches of the clock tree that fanout from some
combinational logic or to exclude an implicit stop pin.

During clock tree synthesis, IC Compiler isolates exclude pins (both implicitand explicit) from
the clock tree by inserting a guide buffer before the pin. Beyond the excludepin, IC Compiler
never performs skew or insertion delay optimization, but does perform designrule fixing.

To specify an exclude pin, use the set_clock_tree_exceptions -exclude_pins
command.

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Floatpins are clock pinsthat have special insertion delay requirements. IC Compiler adds
the float pin delay (positive or negative) to the calculated insertion delay upto this pin.

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Stoppins are the endpointsof the clock tree that are used for delay balancing. During clock
tree synthesis, IC Compiler uses stop pins in calculations and optimizationsfor both design
rule constraints and clock tree timing (skew and insertion delay).

The default clock sinks are implicit stop pins. In addition, IC Compilersupports user-defined
(or explicit) stop pins. For example, you might define a stop pin to end abranch at an input
to a combinational cell or to use an implicit exclude pin as a clock sink.

IC Compiler assigns a phase delay of zero to all stop pins (implicit andexplicit) and uses this
delay during delay balancing.

To specify a stop pin, use the set_clock_tree_exceptions -stop_pinscommand

CTS的全称是Clock Tree Synthesis，其目的是尽可能的使同一个时钟信号到达各个终端节点的时间相同。

CTS的实现办法最常见的是通过在时钟信号的各个分支上插入buffer或者inverter来balance时钟信号的延迟。

Pin结点的类型

Pin类型	别名	备注
exclude pin	ignore pin	不用平衡的节点
stop pin	sync pin	需要平衡的节点
non_stop pin		信号会穿过这个节点
float pin		最终节点”藏“在后面

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近日使用IC Compiler过程中，在做CTS时，发现有一个register的clock pin既是ignorepin又是non-stop pin。

如果是ignore pin，则意味着CTS时应把这个sink排除在外；如果是non-stop pin，则意味着要穿过这个sink。而这两种情况是矛盾的。

研究的结果，发现是由于特殊的clock结构造成的。如下图：

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其中的register被用做二分频，输出端Q通过一个inverter连接到了自己的输入端上；Q端上定义了一个Generated Clock(GCLK)。
因此工具推导出这个register的CLK pin是一个non-stop pin。

同时，这个GCLK通过一个PAD输出到芯片外部，没有再与其他register相连。因些，工具推导出这是一个implicit ignore pin。

知道了原因，解决办法就容易多了。将图中register的CLK pin设置为ignore pin 更为合理些。

不想用generated clock做clock tree
让master clock 一次性全做完clock tree，就要在generated clock的定义点设through pin

就是让clocktree自动穿过的意思， 直到下一个 leafpin

  ICC                            EDI
stop pin                      leaf pin
non_stop_pin          through pin
float_pin                     macromodel
exclude_pin                exclude pin

Alicezw

谢谢楼主辛苦总结，可是图片看不到，而且要是文档就更好了。真是非常感谢呢

200602305121

同意楼上的

hllgreen

写得好，就是看不了图片，强烈要求楼主整理文档呀

pebay888

为什么看不到 图片呢？

pebay888

楼主求图片！！！！

hllgreen

求图片

ra3d

谢谢楼主辛苦总结，可是图片看不到，而且要是文档就更好了。真是非常感谢呢

hongzi_

thanks for shiring

真我个性

有图参见《Clock Tree Pins - Nonstop、Exclude》http://blog.sina.com.cn/s/blog_7a9e76810101frb2.html