请问数据缓冲之后综合频率下降的原因

huarobust · 发表于 2012-11-28 16:18:01

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各位，我写了一段代码，发现RD[29:0]缓冲一个时钟到User_Area_data[29:0]之后综合的平率下降的很多，我想知道原因是什么，谢谢。

没有经过一个时钟延迟的代码

module test(RD,pclk,CMOS_VS,CMOS_HS,y,x,Inter_Use_Area,User_Area_Active,User_Area_Addr);
input [29:0]RD;
input pclk,CMOS_VS,CMOS_HS,User_Area_Active;
input [9:0]y,x;
output reg Inter_Use_Area;
output reg [9:0]User_Area_Addr;
reg [9:0]User_Area_Addr_temp;
reg User_Area_state,Left_IN,Left_OUT;
parameter User_Area_idle=1'b0,User_Area_compare=1'b1;
always @(posedge pclk or negedge CMOS_VS)
if(~CMOS_VS)
begin
User_Area_Addr<=0;
User_Area_state<=User_Area_idle;
end
else
case(User_Area_state)
User_Area_idle:
begin
if(CMOS_HS&&(y==RD[9:0]))
begin
User_Area_state<=User_Area_compare;
User_Area_Addr<=User_Area_Addr_temp;
end
else
User_Area_state<=User_Area_idle;
end
User_Area_compare:
if(x==RD[29:20])
User_Area_state<=User_Area_idle;
else
User_Area_state<=User_Area_compare;
endcase
always @(posedge pclk or negedge CMOS_VS)
if(~CMOS_VS)
begin
User_Area_Addr_temp<=0;
Left_IN<=0;
Left_OUT<=0;
Inter_Use_Area<=0;
end
else
begin
User_Area_Addr_temp<=User_Area_Addr+1;
Left_IN<=x<RD[29:20];
Left_OUT<=x>RD[19:10];
Inter_Use_Area<=Left_IN&&Left_OUT&&User_Area_Active;
end
endmodule

复制代码

综合结果
test|pclk 252.9 MHz 215.0 MHz 3.954 4.652 -0.698 inferred Autoconstr_clkgroup_0
把RD缓冲到User_Area_data的代码

module test(RD,pclk,CMOS_VS,CMOS_HS,y,x,Inter_Use_Area,User_Area_Active,User_Area_Addr);
input [29:0]RD;
input pclk,CMOS_VS,CMOS_HS,User_Area_Active;
input [9:0]y,x;
output reg Inter_Use_Area;
reg [29:0]User_Area_data;
output reg [9:0]User_Area_Addr;
reg [9:0]User_Area_Addr_temp;
reg User_Area_state,Left_IN,Left_OUT;
parameter User_Area_idle=1'b0,User_Area_compare=1'b1;
always @(posedge pclk or negedge CMOS_VS)
if(~CMOS_VS)
begin
User_Area_data<=0;
User_Area_Addr<=0;
User_Area_state<=User_Area_idle;
end
else
case(User_Area_state)
User_Area_idle:
begin
User_Area_data<=RD;
if(CMOS_HS&&(y==User_Area_data[9:0]))
begin
User_Area_state<=User_Area_compare;
User_Area_Addr<=User_Area_Addr_temp;
end
else
User_Area_state<=User_Area_idle;
end
User_Area_compare:
if(x==User_Area_data[29:20])
User_Area_state<=User_Area_idle;
else
User_Area_state<=User_Area_compare;
endcase
always @(posedge pclk or negedge CMOS_VS)
if(~CMOS_VS)
begin
User_Area_Addr_temp<=0;
Left_IN<=0;
Left_OUT<=0;
Inter_Use_Area<=0;
end
else
begin
User_Area_Addr_temp<=User_Area_Addr+1;
Left_IN<=x<User_Area_data[29:20];
Left_OUT<=x>User_Area_data[19:10];
Inter_Use_Area<=Left_IN&&Left_OUT&&User_Area_Active;
end
endmodule

复制代码

综合结果
test|pclk 206.7 MHz 175.7 MHz 4.837 5.691 -0.854 inferred Autoconstr_clkgroup_0

yp19890718 · 发表于 2012-11-28 17:03:59

你用来做缓存,应该是串行引起的关键路径被延迟.

[解决] 请问数据缓冲之后综合频率下降的原因