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Icarus Verilog
http://icarus.com/eda/verilog/
开源VERILOG模拟和综合,LINUX平台
摘要:Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the ``vvp''
command. For synthesis, the compiler generates netlists in the desired format.
Dinotrace
www.veripool.com/dinotrace
模拟波形显示
GTCWave
模拟波形显示
http://www.geda.seul.org/tools/gtkwave/index.html
The Win32 GTKWave Homepage
http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html
VERILATOR
VERILOG模拟,VERILOG转换到C++模型
http://www.veripool.com/verilator.html
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