IC Compiler Design Planning User Guide 2010.03-sp2

shujixyz · 发表于 2012-10-11 10:14:58

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本帖最后由 shujixyz 于 2012-10-11 10:17 编辑

About This Guide

The IC Compiler tool provides a complete netlist-to-GDSII or
netlist-to-clock tree synthesis design solution, which combines
proprietary design planning, physical synthesis, clock tree
synthesis, and routing for logical and physical design implementations
throughout the design flow.

This guide describes the IC Compiler design planning flow;
the companion volume, IC Compiler Implementation User Guide,
describes the implementation and integration flow.

2010--IC+Compiler+Design+Planning+User+Guide.pdf (11.79 MB, 下载次数: 694 )