IC Compiler Design Planning User Guide 2010.03-sp2

shujixyz · 发表于 2012-10-11 10:14:58

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本帖最后由 shujixyz 于 2012-10-11 10:17 编辑

About This Guide

The IC Compiler tool provides a complete netlist-to-GDSII or
netlist-to-clock tree synthesis design solution, which combines
proprietary design planning, physical synthesis, clock tree
synthesis, and routing for logical and physical design implementations
throughout the design flow.

This guide describes the IC Compiler design planning flow;
the companion volume, IC Compiler Implementation User Guide,
describes the implementation and integration flow.

2010--IC+Compiler+Design+Planning+User+Guide.pdf (11.79 MB, 下载次数: 694 )

lyisgrant · 发表于 2012-10-18 14:18:59

thanks so much for that

pansygrass · 发表于 2012-10-19 14:52:10

谢谢谢谢···

lingqi0077 · 发表于 2012-10-22 17:14:08

好东西~感谢楼主

sathya · 发表于 2013-1-1 21:27:47

thanks alot

sallad · 发表于 2013-1-7 09:44:16

thanks very much!

yuanbin · 发表于 2013-1-8 21:16:58

顶起来，好资料

shilldg · 发表于 2013-3-12 22:11:09

最近正在看这个，真真儿的好东西

Hyacinth1292 · 发表于 2013-8-21 08:58:40

下载看看。

li116tao · 发表于 2013-10-30 21:55:55

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[资料] IC Compiler Design Planning User Guide 2010.03-sp2

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

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