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| ABSTRACT (ENGLISH) |
| ACKNOWLEDGEMENTS |
| CONTENTS |
| TABLE CAPTIONS |
| FIGURE CAPTIONS |
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| CHAPTER 1 INTRODUCTION 1 |
| 1.1 Background 1 |
| 1.2 Issue of Mixed-Voltage I/O Interfaces 1 |
| 1.3 Issue of High-Voltage CMOS ICs 4 |
| 1.4 Thesis Organization 5 |
| Figures 7 |
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| CHAPTER 2 OVERVIEW ON ESD PROTECTION DESIGN FOR MIXED-VOLTAGE I/O CIRCUITS 11 |
| 2.1 Substrate-Triggered Stacked-NMOS Device 11 |
| 2.2 Extra ESD Device between I/O Pad and VSS 13 |
| 2.3 Extra ESD Device between I/O Pad and VDD 15 |
| 2.4 ESD Protection Design with ESD Bus 16 |
| 2.5 Special Applications 17 |
| 2.6 Summary 18 |
| Figures 19 |
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| CHAPTER 3 ESD PROTECTION DESIGN WITH LOW-VOLTAGE-TRIGGERED PNP (LVTPNP) DEVICES FOR MIXED-VOLTAGE I/O INTERFACE |
| 25 |
| 3.1 ESD Protection Design with LVTPNP Device 25 |
| 3.1.1 Device Structures and TLP-Measured I-V Characteristics 26 |
| 3.1.2 Layout Parameters of LVTPNP Devices on HBM ESD Levels 27 |
| 3.1.3 Multi-Finger Layout Style for LVTPNP 29 |
| 3.2 Application in ADSL Interface 31 |
| 3.2.1 ESD Protection Design with LVTPNP for Input Stage of ADSL 31 |
| 3.2.2 HBM ESD Levels of ADSL with the Type3 LVTPNP 33 |
| 3.2.3 Failure Analysis 34 |
| 3.3 Summary 34 |
| Tables 36 |
| Figures 40 |
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| CHAPTER 4 HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT IN LOW-VOLTAGE THIN-OXIDE TECHNOLOGY 55 |
| 4.1 ESD Protection Scheme for Mixed-Voltage I/O Interface 55 |
| 4.2 High-Voltage-Tolerant ESD Clamp Circuit 57 |
| 4.2.1 Substrate-Triggered STNMOS 57 |
| 4.2.2 Operation Principle 58 |
| 4.2.3 H-Spice Simulated Results 59 |
| 4.3 Experiment Results 60 |
| 4.3.1 Characteristics of Substrate-Triggered STNMOS 60 |
| 4.3.2 Turn-on Speed 61 |
| 4.3.3 ESD Robustness of STNMOS Devices 62 |
| 4.4 Summary 62 |
| Tables 63 |
| Figures 64 |
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| CHAPTER 5 ESD PROTECTION DESIGN FOR AUTOMOTIVE VACUUM-FLUORESCENT-DISPLAY (VFD) DRIVER IC 72 |
| 5.1 Original Design for VFD I/O 72 |
| 5.1.1 Device Structure and I-V Characteristic of the HVPMOS 73 |
| 5.1.2 ESD robustness and Failure Analysis 73 |
| 5.2 New ESD Design for VFD I/O 74 |
| 5.2.1 Device Structure and Turn-on Mechanism of the HVPSCR 74 |
| 5.2.2 ESD Protection Design for VFD I/O with Both HVPSCR and |
| Power-Rail ESD Clamp Circuit 76 |
| 5.3 Experimental Results 77 |
| 5.3.1 I-V Characteristic of the HVPSCR 77 |
| 5.3.2 ESD robustness of the VFD Driver IC 79 |
| 5.4 Summary 79 |
| Tables 81 |
| Figures 82 |
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| CHAPTER 6 ESD ROBUSTNESS OF ON-CHIP ESD PROTECTION DEVICES IN 40-V CMOS TECHNOLOGY 96 |
| 6.1 Device Structures in 40-V CMOS Process 96 |
| 6.1.1 HV NMOS With or Without N-Drift Implant 97 |
| 6.1.2 HV PMOS With or Without P-Drift Implant 97 |
| 6.1.3 HVNSCR With or Without N-Drift Implant 98 |
| 6.2 Experimental Results and Discussion 99 |
| 6.2.1 TLP-Measured I-V Characteristics 99 |
| 6.2.2 HBM ESD Robustness 103 |
| 6.2.3 Failure Analysis 105 |
| 6.3 Summary 105 |
| Tables 106 |
| Figures 107 |
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| CHAPTER 7 CONCLUSIONS AND FUTURE WORK 120 |
| 7.1 Main Results of This Thesis 120 |
| 7.2 Future Works 122 |
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| REFERNCES 123 |
| VITA 131 |
| PUBLICATION LIST 132
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