新手请教：IP核（eeprom）的时序问题

禅师1988 · 发表于 2012-9-4 16:06:21

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本帖最后由禅师1988 于 2012-9-4 16:07 编辑

设计中包含一个EEPROM，用DC综合以及astro布局布线都没有时序问题，但是用encounter就显示eeprom的延时过大，
encounter时序分析如下：
捕获.PNG

可见eeprom的PRE_CHG到EEDBO1的延时很大，而我的时钟周期只有140，造成严重违例，而从lib中的信息来看，这个延时信息没错啊，我的问题是为什么DC和astro中都没有报错，即为什么没有考虑eeprom这个延时？？

下面是eeprom的lib中的信息：
pin(EEDBO1) {
   direction : output ;
   function :  "  PRE_CHG " ;
   capacitance : 0.000000 ;
   max_capacitance : 0.714032 ;
   timing() {
      related_pin : "PRE_CHG" ;
      cell_rise(Table1) {
      values(\
               "10000.019531, 10000.059570, 10000.089844, 10000.169922",\
               "10000.330078, 10000.370117, 10000.400391, 10000.480469",\
               "10001.580078, 10001.629883, 10001.660156, 10001.730469",\
               "10003.150391, 10003.190430, 10003.219727, 10003.299805",\
               "10004.709961, 10004.759766, 10004.790039, 10004.860352"\
      );
      }
      rise_transition(Slew1) {
      values(\
               "4.482940, 8.836245"\
      );
      }
      cell_fall(Table1) {
      values(\
               "10000.019531, 10000.070312, 10000.099609, 10000.169922",\
               "10000.349609, 10000.400391, 10000.429688, 10000.500000",\
               "10001.639648, 10001.690430, 10001.719727, 10001.790039",\
               "10003.250000, 10003.299805, 10003.330078, 10003.400391",\
               "10004.870117, 10004.919922, 10004.950195, 10005.019531"\
      );
      }
      fall_transition(Slew1) {
      values(\
               "3.214440, 6.280863"\
      );
      }
   }
}

陈涛 · 发表于 2012-9-4 16:39:31

打开DC，报同样的path，比较结果，找原因

禅师1988 · 发表于 2012-9-4 19:05:31

回复 2# 陈涛

这是DC报的该路径的时序分析，可见DC认为eeprom延时为0……

Startpoint: eeprom_control/state_reg_3_
            (rising edge-triggered flip-flop clocked by clock)
  Endpoint: read_write_compare_c/state_reg_1_
         (rising edge-triggered flip-flop clocked by clock)
  Path Group: clock
  Path Type: max

  Point                                                 Incr    Path
  --------------------------------------------------------------------------
  clock clock (rise edge)                               0.00    0.00
  clock network delay (propagated)                      5.47    5.47
  eeprom_control/state_reg_3_/H02 (F612NQ)             0.00    5.47 r
  eeprom_control/state_reg_3_/N01 (F612NQ)             2.92    8.40 r
  eeprom_control/U87/N01 (F202)                         0.48    8.88 f
  eeprom_control/U86/N01 (F202N1)                      1.15    10.03 f
  eeprom_control/U85/N01 (L302)                         0.50    10.54 r
  eeprom_control/U131/N01 (L101)                         0.51    11.05 f
  eeprom_control/pre_charge (eeprom_control)             0.00    11.05 f
  HMEEPSF256B00V3/EEDBO1 (HMEEPSF256B00V3)             0.00    11.05 f
  eeprom_control/EEDBO1 (eeprom_control)                0.00    11.05 f
  eeprom_control/U153/N01 (F111)                         0.91    11.96 f
  eeprom_control/data_from_rom[1] (eeprom_control)       0.00    11.96 f
  read_write_compare_c/data_from_rom[2] (read_write_compare)
                                                      0.00    11.96 f
  read_write_compare_c/sll_198_2/A[1] (read_write_compare_DW01_ash_0)
                                                      0.00    11.96 f
  read_write_compare_c/sll_198_2/M1_0_2/N01 (L565)       2.20    14.16 f
  read_write_compare_c/sll_198_2/M1_1_2/N01 (Y565)       2.46    16.62 f
  read_write_compare_c/sll_198_2/M1_2_6/N01 (Y565)       2.43    19.06 f
  read_write_compare_c/sll_198_2/U19/N01 (L312)          1.06    20.11 f
  read_write_compare_c/sll_198_2/B[6] (read_write_compare_DW01_ash_0)
                                                      0.00    20.11 f
  read_write_compare_c/U234/N01 (L512)                   1.12    21.23 r
  read_write_compare_c/U238/N01 (L318)                   2.17    23.39 r
  read_write_compare_c/U286/N01 (L312)                   1.12    24.52 r
  read_write_compare_c/U10/N01 (L434)                   0.48    25.00 f
  read_write_compare_c/U97/N01 (Y216)                   3.57    28.57 f
  read_write_compare_c/U98/N01 (Y101)                   0.74    29.32 r
  read_write_compare_c/U102/N01 (Y212)                   1.02    30.33 r
  read_write_compare_c/U103/N01 (Y101)                   0.51    30.84 f
  read_write_compare_c/state_reg_1_/H01 (L612NQ)       0.00    30.84 f
  data arrival time                                              30.84

  clock clock (rise edge)                            140.00    140.00
  clock network delay (propagated)                      5.47    145.47
  clock uncertainty                                     -0.35    145.12
  read_write_compare_c/state_reg_1_/H02 (L612NQ)       0.00    145.12 r
  library setup time                                  -2.23    142.89
  data required time                                              142.89
  --------------------------------------------------------------------------
  data required time                                              142.89
  data arrival time                                              -30.84
  --------------------------------------------------------------------------
  slack (MET)                                                    112.05