关于AHB的两个问题

ddongq

最近在看AMBA spc，其中有两个地方想不通为什么，网上也没搜到答案，所以来这里问问有经验的前辈：
1.  spc上有这样的描述："In very high clock frequency systems it may become necessary for the bridge to register the read data at the end of the ENABLE cycle and then for the bridge to drive this back to the AHB bus master in the following cycle.  although this will require an extra wait state for peripheral bus read transfers, it allows the AHB to run at a higher clock
frequency, thus resulting in an overall improvement in system performance. "我的疑问是为什么bridge将读数据寄存一拍然后再驱动回AHB bus master可以使AHB跑在更高的频率上？
2.  spc上有这样的描述：“After a sequence of locked transfers the arbiter will always keep the bus master granted for an additional transfer to ensure that the last transfer in the locked sequence has
completed successfully and has not received either a SPLIT or RETRY response. Therefore it is recommended, but not mandatory, that the master inserts an IDLE transfer after any locked sequence to provide an opportunity for the arbitration to change before commencing another burst of transfers.”我的疑问是为什么这样建议呢？想不通啊~
请对这些理解比较深的前辈们给讲讲啊，谢谢！

lswei001

都是大牛啊，期待牛人跟贴

angel318393

这个帖子不错，大家快来顶起来！

cuimingzhi

简单化，存一拍可以实现一级流水。 pipeline.

wuleter

1，如4楼所说bridge锁存下，减少组合逻辑长度，提升速率
2、多一个idle等待response后再发新命令吧，这样可以避免收到split、retry后lock重新arbiter吧
不一定对，供参考。
话说现在用ahb的不多吧，我都不清这些了。。

engbe

1.流水线

Holtek12

組合邏輯遇到 latency 長的時候, DFF latch 一級, 再向後推, 可以避免此 latency 成為整體設計的 bottleneck.