请问一下systemverilog 断言中assume 和assert的区别

timxavier

SystemVerilog 上的解释：
The immediate  assume statement specifies that its expression is assumed to hold. For example, immediate
assume statements can be used with formal verification tools to specify assumptions on design inputs that
constrain the verification computation. When used in this way, they specify the expected behavior of the
environment of the design as opposed to that of the design itself. In simulation, an immediate assume may
behave as an immediate  assert to verify that the environment behaves as assumed. A simulation tool shall
provide the capability to check the immediate  assume statement in this way.


仿真时，assert与assume用途一样
形式验证时，assume可用于约束DUT的输入，用于过滤不需要的时序组合

timxavier

回复 11# timxavier

6楼的例子就是这样assume用于约束p，防止状态爆炸

闪闪的星辉

回复 1# interlm


    LOUZHUJIAYOU

lpandlly

assume 相当于约束, 就是假设条件成立

iNostory

形式验证时，assume可用于约束DUT的输入，用于过滤不需要的时序组合