求各位大牛帮忙看看

tangyutao

本人用的是spartan6板子的，用IP核产生个时钟输出。可是每次到综合就出现这样错误
ERRORlace:1206 - This design contains a global buffer instance,
   <instance_name/clkout1_buf>, driving the net, <clk_out_OBUF>, that is driving
   the following (first 30) non-clock source pins off chip.
   < PIN: clk_out.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "instance_name/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

ERRORlace:1136 - This design contains a global buffer instance,
   <instance_name/clkout1_buf>, driving the net, <clk_out_OBUF>, that is driving
   the following (first 30) non-clock source pins.
   < PIN: clk_out.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "instance_name/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >

Phase 2.7  Design Feasibility Check (Checksum:4fdeefbf) REAL time: 5 secs

Total REAL time to Placer completion: 5 secs
Total CPU  time to Placer completion: 5 secs
ERRORack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file "clk_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   3
Number of warnings :   0

Process "Map" failed

nikalew

朋友，你的问题解决了吗？怎么解决的啊，我也碰到相同的问题了，想分倍频时钟作为外部时钟，综合老是报和你相同的错。

yangyuf1

解决办法：
1）：修改设计。不让global clock 驱动一般的组合逻辑。只驱动DFF的clock pin.
2）：在UCF中设置： PIN "instance_name/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 这个ISE的error log中有提示。
3）：按照ISE error log中的另一种方法修改。

liujilonghit201

赛灵思官网上这么一个例子，3225，得用到ODDR2

wuhuafu

我也在学这个，不知道怎么搞，求大神