关于sram的testbench怎么写 ？有原程序。。。求指导。。。

lixuecheng

1. module sram(clk_50,reset,sram_addr,wr_en,cs_n,oe_n,ub_n,lb_n,led,sram_data);//control the sram and test in the led
   
2. input clk_50;
   
3. input reset;
   
4. output [19:0] sram_addr;
   
5. output wr_en,cs_n,oe_n,ub_n,lb_n,led;
   
6. inout [15:0] sram_data;
   
7. 
   
8. assign cs_n=1'b0;//chip selet enable
   
9. assign oe_n=1'b0;// output enable
   
10. assign ub_n=1'b0;//upper byte avaliable
    
11. assign lb_n=1'b0;//lower byte avaliable
    
12. 
    
13. reg[25:0] delay;//delay 0.02us*2^26=1.34s
    
14. clk_50 or negedge reset)
    
15. if(!reset)
    
16. delay<=26'b0;
    
17. else
    
18. delay<=delay+1'b1;
    
19. 
    
20. reg[15:0] wr_data;
    
21. reg[15:0] rd_data;
    
22. reg[19:0] addr_r;
    
23. 
    
24. wire  wr_req;
    
25. wire rd_req;
    
26. reg led_r;
    
27. 
    
28. assign wr_req=(delay==26'd9999);
    
29. assign rd_req=(delay==26'd19999);
    
30. 
    
31. always @(posedge clk_50 or negedge reset)
    
32. if(!reset)
    
33. wr_data<=16'd0;
    
34. else if(delay==26'd29999)
    
35. wr_data<=wr_data+1'b1;
    
36. always @(posedge clk_50 or negedge reset)
    
37. if(!reset)
    
38. addr_r<=20'd0;
    
39. else if(delay==26'd29999)
    
40. addr_r<=addr_r+1'b1;
    
41. always @(posedge clk_50 or negedge reset)
    
42. if(!reset)
    
43. led_r<=1'b0;
    
44. else if(delay==26'd29999)
    
45. begin
    
46.   if(wr_data==rd_data)
    
47.   led_r<=1'b1;
    
48.   else
    
49.   led_r<=1'b0;
    
50. end
    
51. assign led=led_r;
    
52. 
    
53. reg[2:0]cnt;
    
54. `define delay_80ns (cnt==3'd7)  //delay 0.02us*7=140ns
    
55. 
    
56. reg[3:0] state,nextstate;
    
57. 
    
58. parameter idle =4'd0;
    
59. parameter writ0 =4'd1;
    
60. parameter writ1 =4'd2;
    
61. parameter rea0 =4'd3;
    
62. parameter rea1 =4'd4;
    
63. 
    
64. 
    
65. always @(posedge clk_50 or negedge reset)
    
66. if(!reset)
    
67. cnt<=3'd0;
    
68. else if(state==idle)
    
69. cnt<=3'd0;
    
70. else
    
71. cnt<=cnt+1'b1;
    
72. clk_50 or negedge reset)
    
73. if(!reset)
    
74. state<=idle;
    
75. else
    
76. state<=nextstate;
    
77. clk_50 or negedge reset)
    
78. case(state)
    
79. idle: if(wr_req)
    
80.   nextstate<=writ0;
    
81.   else if(rd_req)
    
82.   nextstate<=rea0;
    
83.   else nextstate<=idle;
    
84. writ0:if(`delay_80ns)
    
85.   nextstate<=writ1;
    
86.   else nextstate<=writ0;
    
87. writ1: nextstate<=idle;
    
88. rea0:if(`delay_80ns)
    
89.   nextstate<=rea1;
    
90.   else nextstate<=rea0;
    
91. rea1:nextstate<=idle;
    
92. endcase
    
93. assign sram_addr=addr_r;
    
94. 
    
95. //  lock data
    
96. reg sdlink;     //SRAM address control
    
97. clk_50 or negedge reset)
    
98.     if(!reset)
    
99.         rd_data <= 16'b0;
    
100.     else if(state == rea1)
     
101.         rd_data <= sram_data;
     
102.          
     
103. clk_50 or negedge reset)
     
104.     if(!reset)
     
105.         sdlink <= 1'b0;
     
106.     else
     
107.         case(state)
     
108.             idle:   if(wr_req)
     
109.                         sdlink <= 1'b1;
     
110.                     else if(rd_req)
     
111.                         sdlink <= 1'b0;
     
112.                     else
     
113.                         sdlink <= 1'b0;
     
114.             writ0:   sdlink <= 1'b1;
     
115.             default:sdlink <= 1'b0;
     
116.         endcase
     
117.       
     
118. assign sram_data = sdlink ? wr_data:16'hzzzz;
     
119. assign wr_en = ~sdlink;
     
120.   
     
121. endmodule
     
122. 
     
123. 
     
124. 
     

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lixuecheng

http://archive.cnblogs.com/a/2258208/   原文链接在这 希望大牛帮忙看看 写个测试文件 。。。这inout口搞死我了。。。。我写的测试文件不出波形。。。。

tigerjade

sram_data = sdlink ? wr_data:16'hzzzz;
这句话反过来不就是你testbench的输入?

小小舟

先支持一下

zrseu

顶顶顶顶

mangotango

any other much complete?