求租verilog程序，大神看看我写的，密码锁

xs303532644

仿真不出来啊，密码是ascii码的 zhangyx，是哪写错了么？？
module test(rst,clk,cmd,cancel,enter,pass);
input clk;
input rst;
input [7:0]cmd;
wire [7:0]cmd;
input cancel,enter;
output pass;
wire pass;
reg ok;
reg [2:0]d;
reg [20:0]password;
reg [2:0]state;
parameter PASSWORD=21'b111110101100011010001;
parameter  st0=3'd0,

st1=3'd1,

st2=3'd2,

st3=3'd3,

st4=3'd4,

st5=3'd5,

st6=3'd6,

st7=3'd7;            

always @ (cmd)
  begin
       begin
     case(cmd)
   8'b01111010: d<=3'd1;   //z
   8'b01101000: d<=3'd2;   //h
   8'b01100001: d<=3'd3;   //a
   8'b01101110: d<=3'd4;   //n
   8'b01100111: d<=3'd5;   //g
   8'b01111001: d<=3'd6;   //y
   8'b01111000: d<=3'd7;   //x
default: d<=3'd0;
   endcase
end
end

always @(posedge clk)
if(rst)
begin
   ok<=0;
   password<=0;
   state<=st0;
end

else
   case(state)

0:begin
      ok<=0;
      password[20:18]<=d;
      state<=st1;
     end

1:if(cancel)
       begin
      password<=0;
      state<=st0;
       end

else
    begin
      password[17:15]<=d;
      state<=st2;
    end

2:if(cancel)
    begin
     state<=st1;

end
     else
    begin
     password[14:12]<=d;
     state<=st3;
    end

3:if(cancel)
     state<=st2;
   else
    begin
    password[11:9]<=d;
    state<=st4;
   end

4:if(cancel)
     state<=st3;
   else
    begin
    password[8:6]<=d;
    state<=st5;
   end

5:if(cancel)
     state<=st4;
   else
    begin
    password[5:3]<=d;
    state<=st6;
   end

6:if(cancel)
     state<=st5;
   else
    begin
    password[2:0]<=d;
    state<=st7;
   end

7:if(enter)
    if(password==PASSWORD)
      begin
      ok<=1;
      end
   else
     state<=st0;
     
default:
        begin
        ok<=0;
        state<=st0;
        password<=0;
        end

endcase
assign pass=(ok==1)?1:0;
endmodule

duan_dzj

state的赋值搞错了。不是你定义的0...7一类。而是st0.反正你的case内部赋值和外部跳转赋值必须一致。

henryshen2000

粗看是密码颠倒了，输入“xygnahz”就可以Pass了！