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发表于 2012-4-26 14:53:58
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//**************************************************************************
// Title : CZ6H+/CZ6L+ CALIBRE DRC RULEFILE for HHNEC 0.35um 1P4M 5.0V PROCESS
// Reference Document : DM-CZ6H-0837-020(DR),DM-CZ6H-0838-020(DF),
// DM-CZ6H-0845-020(ESD)
// Command Document : DM-CZ6H-0878-020
// Revision : 2.0
// Released By : P.Li , 2011/04/01 Design Support Dept. HHNEC
//**************************************************************************
//
// DISCLAIMER
//
// The information contained herein is provided by HHNEC on an "AS IS" basis
// without any warranty, and HHNEC has no obligation to support or otherwise
// maintain the information. HHNEC disclaims any representation that the
// information does not infringe any intellectual property rights or proprietary
// rights of any third parties. There are no other warranties given by HHNEC,
// whether express, implied or statutory, including, without limitation, implied
// warranties of merchantability and fitness for a particular purpose.
//
// STATEMENT OF USE
//
// This information contains confidential and proprietary announcement of HHNEC.
// Unauthorized reproduction, distribution to any human or computer language,
// storation in a retrieval system, in any form or by any means, electronics,
// mechanical, magnetic, optical, chemical, manual, or otherwise, will be
// procecuted to the maxium extent possible under the law. This information
// was prepared for informational purpose and is for use by HHNEC's customers
// only. HHNEC reserves the right to make changes in the information at any
// time and without notice.
//
//***************************************************************************
//
// Revision History:
// 2.0 2011/04/22 P Li
// Initial Release
//
//**************************************************************************
//
// NOTICE: (Read Me First!)
//
// 1. The runset is tested and developed on Calibre ver 2004.2_5.19
// please use this or newer version of Calibre to execute this runset.
// 2. The maximun number of same type of errors reported is 1000 by default
// because the command "DRC MAXIMUM RESULTS 1000" is set.
// 3. The following rules are not implemented
// 1) design rules for pad area
// 2) Pch.L,Nch.N
// 3) Thermal Cycle protection (Page 38)
// 4. Pls notice:
// 1) POLY.d2 maybe have some false error, pls waive
// 2) Pch.E,Pch.F will skip some error when the space > 4.56,1.8 in asymmetry
// structure.
// 3) Slot size(SLOT.L.W) will be report false error for "L" structure in corner
// 4) Only check 150mA guardring rules
// 5) Nch.I maybe have some false error when one drain not have two sourc
// 5. For different thick metal check,pls change the switch on Line 67 for 9K,12K,30K thick metal
// 6. For hhnec internal use about some special device, pls open the swith on
// Line 99
//
//**************************************************************************
//|-------------------|
//| Top metal choose |
//|-------------------|
#DEFINE TME9K //0.9um thickness top metal
// #DEFINE TME12K //1.2um thickness top metal
//#DEFINE TME30K //3um thickness top metal
//|-------------------|
//| ENVIRONMENT SETUP |
//|-------------------|
PRECISION 1000
RESOLUTION 10 // tool resolution
LAYOUT SYSTEM GDSII
LAYOUT PATH "TOPCELL.gds"
LAYOUT PRIMARY "TOPCELL"
DRC RESULTS DATABASE "DRC.db"
DRC SUMMARY REPORT "DRC.rep"
FLAG OFFGRID YES // For layout grid check. default grid value is resolution size
FLAG ACUTE YES
FLAG SKEW YES
FLAG NONSIMPLE YES
DRC CHECK TEXT ALL
DRC MAXIMUM RESULTS 1000
//|------------------------------|
//| Switch for hhnec internal use|
//|------------------------------|
// #DEFINE IN_USE
//|-------------------------|
//| DRAWN LAYER DEFINITIONS |
//|-------------------------|
LAYER NWEL 1 // NWELL nwell technology
LAYER NDi 2 // NDIFF N+ Diffusion
LAYER PPOLY 4 // PPOLY polysilicon Pch
LAYER COT 5 // COT Contact Metal-1 to Diff/Poly
LAYER ME1 6 // ME1 Metal 1
LAYER COVER 7 // COVER Passivation/Overlay
LAYER MCAP 10 // MCAP Metal Capacitance
LAYER RPOLY 11 // RPOLY Polysilicon Resistance
LAYER IOPW 13 // IOPW P-Well in IO area
LAYER V3 17 // V3 Via-3 Hole
LAYER PDi 22 // PDIFF P+ Diffusion
LAYER NPOLY 24 // NPOLY Polysilicon Nch
LAYER NWC 25 // NWC Gate Capacitor on N-well
LAYER FRAME 29 // CELF Cell Frame and scribe center
LAYER NWR 30 // NWR Resistor by N-well
LAYER IONW 31 // IONW N-Well in IO area
LAYER PWEL 32 // PWEL P-Well
LAYER ROMC 33 // ROMC Rome Code
LAYER RESID 34 // RESID Resistance for LVS
LAYER X35 35 // From dracula layer
LAYER ME2 36 // ME2 Metal 2
LAYER V1 37 // V1 Via 1 Hole
LAYER VTN0 38 // VTN0 Nch Nondope
LAYER ME3 40 // ME3 Metal 3
LAYER V2 41 // V2 Via 2 Hole
#IFDEF TME9K
LAYER TOPME 42 // TTME9 0.9um Thickness Top metal
#ENDIF
#IFDEF TME12K
LAYER TOPME 138 // TME12K 1.2umthickness thick top metal
#ENDIF
#IFDEF TME30K
LAYER TOPME 16 // TTME3 3um thickness thick top metal
#ENDIF
LAYER GRID 136 // GRID guardring area
LAYER IOID 144 // IOID IO area
LAYER SLTID 109 // SLTID slot ID area
LAYER DNWX 53 // DNW deep nwell
LAYER ME1OBS 66 // ME1OBS ME1 OBS
LAYER ME2OBS 67 // ME2OBS ME2 OBS
LAYER ME3OBS 68 // ME3OBS ME3 OBS
LAYER L20 20 //
LAYER L57 57 //
LAYER L45 45 //
LAYER L46 46 //
LAYER L80 80 //
LAYER L51 51 //
LAYER L52 52 //
LAYER L79 79 //
LAYER CAP1FF 157 // 1ff/um^2 capmim mark layer
LAYER RID2K 149 // 2K Rpoly Resistor Marking Layer
LAYER RID10K 150 // 10K Rpoly Resistor Marking Layer
LAYER FUSEID 130 // mark layer for fuse
LAYER SB 64 // silicide block
LAYER DVTN 85 // Depleted NMOS device VT implant
TEXT DEPTH ALL
TEXT LAYER 28
TEXT LAYER 63
TEXT LAYER 65
TEXT LAYER 6 36 40 TOPME
ATTACH 6 ME1
ATTACH 36 ME2
ATTACH 40 ME3
ATTACH TOPME TOPME
LAYOUT TOP LAYER TOPME V3 ME3 V2 ME2 V1 ME1
LABEL ORDER TOPME ME3 ME2 ME1 ALLPOLY_T PSD NSD NWEL NWR NWC
CONNECT TOPME ME3 BY V3
CONNECT ME3 ME2 BY V2
CONNECT ME2 ME1 BY V1
CONNECT NTAP ME1 BY COT
CONNECT PTAP ME1 BY COT
CONNECT NWRTAP ME1 BY COT
CONNECT NWCTAP ME1 BY COT
CONNECT NSD ME1 BY COT
CONNECT PSD ME1 BY COT
CONNECT ALLPOLY_T ME1 BY POLYCOT
CONNECT RPOLY_T ME1 BY COT
SCONNECT NWRTAP NWR
SCONNECT NWCTAP NWC
CONNECT ME1 MCAP BY MCAPCOT
SCONNECT NTAP NWEL
SCONNECT NTAP IONW
CONNECT NSD PTAP
CONNECT PSD NTAP
//|---------------------------------------|
//| GLOBAL DERIVED LAYERS FOR RULE CHECKS |
//|---------------------------------------|
CHIP = EXTENT
BULK = SIZE CHIP BY 1.0
DIFFi = PDi OR NDi
DIFF = PD OR ND
WELL = NWEL OR PWEL
POLY = ALLPOLY NOT INTERACT IOWEL
PGT = ALLPOLY AND PDIFF
NGT = ALLPOLY AND NDIFF
GT = PGT OR NGT
PSD = PDIFF NOT GT
NSD = NDIFF NOT GT
SCOT = COT NOT LCOT
LCOT = COT INSIDE RPOLY
MCAPCOT = COT INTERACT MCAP
POLYCOT = (COT NOT MCAPCOT) INTERACT ALLPOLY
RPOLY_T = RPOLY NOT RESID
ALLPOLY_T = ALLPOLY NOT RESID
//|Doughnut type and Normal type
PDHOLE = HOLES (PDIFF OR L45) EMPTY //from dracula
NDHOLE = HOLES (NDIFF OR L45) EMPTY //from dracula
DIFFHOLE = HOLES (DIFF OR L45) EMPTY
PTHOLE = HOLES PTAP EMPTY
NTHOLE = HOLES NTAP EMPTY
PDNUT = TOUCH PD PDHOLE //Doughnut type Diff
NDNUT = TOUCH ND NDHOLE //Doughnut type Diff
//|In same well and in diff well
ND = NDi NOT RESID
PD = PDi NOT RESID
PDIFF = PD AND ANWELL
NDIFF = ND NOT ANWELL
PDIFFi = PDi AND ANWELL
NDIFFi = NDi NOT ANWELL
NBUT = TOUCH ND PD //get N+ butting diff
PBUT = TOUCH PD ND //get P+ butting diff
NBUT_E = ND TOUCH EDGE PD
PBUT_E = PD TOUCH EDGE ND
NTAP = (ND AND ANWELL) NOT ALLPOLY
PTAP = (PD NOT ANWELL) NOT ALLPOLY
//|DIFF in NWR and NWC
NWRTAP = ND INTERACT NWR //Get NWRTAP
NWCTAP = ND INTERACT NWC //Get NWCTAP
ALLPOLY = NPOLY OR PPOLY
IOWEL = IOPW AND IONW
DNW = IOWEL INSIDE ND
NWD = IOWEL NOT DNW
ANWELL = ((NWEL OR IONW) OR NWR) OR NWC
PGATE = ALLPOLY AND PD
NGATE = ALLPOLY AND ND
GATE = PGATE OR NGATE
NGATE_TR = NGATE NOT ANWELL
PGATE_TR = PGATE AND ANWELL
GATE_TR = NGATE_TR OR PGATE_TR
NNDNW = NWD WITH TEXT "U%%NNON"
NCDNW = NWD WITH TEXT "U%%NCODE"
DAREA = ALLPOLY OR ((PD OR NWR) OR NWD)
NWR_T = DAREA WITH TEXT "U%%NWRES"
POR = DAREA WITH TEXT "U%%PORES"
POLYRR = ALLPOLY AND POR
RNW = NWR AND NWR_T
/////////////////////////////////////////////////////////
//Nch ///////////////////////////////////////////////////
/////////////////////////////////////////////////////////
NBNW = NWD WITH TEXT "U%%NBUF" //N buffer N wel
//PWH = HOLES PWEL
PWH = HOLES PD INNER EMPTY
NBPWH = PWH ENCLOSE NBNW
NBPW = TOUCH PD NBPWH
NBNF = NBFS OR NBFD
NBPF = PD AND NBPW
NBFD = ND INSIDE NBNW //N buffer field d
NBFS = ND CUT NBNW //N buffer field s
NBNFSL = SIZE NBNF BY 0.3
NBNFSS = SIZE NBNFSL BY -0.3
NBPOLY_1 = ALLPOLY AND NBFS
NBPOLY = ALLPOLY ENCLOSE NBPOLY_1
NBFDCOT = COT AND NBFD
NBFSCOT = COT AND NBFS
NBPFCOT = COT AND NBPF
/////////////////////////////////////////////////////////
//Pch ///////////////////////////////////////////////////
/////////////////////////////////////////////////////////
PBPF = PD WITH TEXT "U%%PBUF" //P buffer P+ field PSD
PBNW = NWEL ENCLOSE PBPF //P buffer N well
PBNF = PBNW AND ND //P buffer n+ field NTAP
PBGT = PBPF AND ALLPOLY //P buffer Gate
PBSD = PBPF NOT PBGT //P buffer source and drain
PBSDCT = COT AND PBSD
PBNFCT = COT AND PBNF
PBPF_PARA = PBPF TOUCH EDGE PBGT
PBPF_PERP = PBPF NOT TOUCH EDGE PBGT
/////////////////////////////////////////////////////////
//Pch //////////get source and drain/////////////////////
/////////////////////////////////////////////////////////
PBSP = PBSD TOUCH PBGT == 1 //Select Source on the end side
PBSPC = PBSP AND COT //Select cot on sorce of the end side
TMP1:2 = ME1 ENCLOSE PBSPC //Select ME1 connect to source cot on the end side
TMP2:1 = TMP1:2 AND V1 //Select V1 connect to ME1
TMP3 = ME2 ENCLOSE TMP2:1 //Select ME2 connect to V1
TMP4 = TMP3 AND V2 //Select V2 connect to ME2
TMP5 = ME3 ENCLOSE TMP4 //Select ME3 connect to V2
TMP6 = TMP5 AND V2 //Select All V2 connect to ME3
TMP7 = ME2 ENCLOSE TMP6 //Select All ME2 connect to V2
TMP8 = TMP3 OR TMP7
TMP9 = TMP8 AND V1
TMPA = ME1 ENCLOSE TMP9
PBSAL1 = TMP1:2 OR TMPA
TMPB = PBNF AND COT
TMPC = ME1 ENCLOSE TMPB
PBSAL2 = TMPC OR PBSAL1
PBSC = PBSAL2 AND COT //COT Connect to Source
PBD = PBSD NOT ENCLOSE PBSC //Drain
PBS = PBSD ENCLOSE PBSC //Source
PBDCT = PBD AND COT //Drain Cot
PBSCT = PBS AND COT //Source Cot
/////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
//OBS////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
ALLNW = (NWEL OR NWC) OR NWR
ME_OBS = (ME1OBS OR ME2OBS) OR ME3OBS
//|------------|
//|NW CHECKS |
//|------------|
GROUP GNW NW?
DIFF_IN_NW = DIFFi AND NWEL
DIFF_NOT_NW = DIFFi NOT NWEL
NW.a1 { @ Min. NWEL width 1.2um
INT NWEL < 1.2 ABUT <90 SINGULAR REGION
}
NW.a2 { @ Min. same potential NWEL space 1.2um
EXT NWEL < 1.2 ABUT <90 SINGULAR REGION CONNECTED
}
NW.a3 { @ Min. different potential NWEL space 3.6um
EXT NWEL < 3.6 ABUT <90 SINGULAR REGION NOT CONNECTED
}
NW.a4.a5 { @ Min. enclosure of NW to P+ diffusion is 0.6um
@ Min. enclosure of NW to N+ diffusion is 0.6um
ENC DIFF_IN_NW NWEL < 0.6 ABUT<90 SINGULAR REGION
}
NW.a6.a7 { @ Min. external of NW to P+ diffusion is 1.8um
@ Min. external of NW to N+ diffusion is 1.8um
A = DIFF_NOT_NW NOT ALLPOLY
B = EXT A NWEL < 1.8 ABUT<90 SINGULAR REGION
C = (HOLES NWEL INNER) AND DNWX
D = (C ENCLOSE ((HOLES PTAP INNER) ENCLOSE (NDIFF NOT INTERACT ALLPOLY))) NOT INTERACT X35
B NOT D
}
NW.a8 { @ PROHIBITE OVERLAP NWELL AND NWELL(ACCSR)
@ This rule is according to dracula E62 (chk1.dra.cz6h)
AND NWEL IONW
}
NW.a9 { @ PROHIBITE LVS RESI ON NWELL(ACCSR)
@ This rule is according to dracula E61 (chk1.dra.cz6h)
A = RESID OUTSIDE ( RESID AND ND )
A AND IONW
}
//|------------|
//|DIFF CHECKS |
//|------------|
GROUP GDIFF DIFF?
DIFF.c1 { @ Min. width of diffusion is 0.75um
INT DIFFi < 0.75 ABUT<90 SINGULAR REGION
}
DIFF.c2 { @ Min. spacing of same type diff is 0.48um
EXT NDi < 0.48 ABUT<90 SINGULAR REGION
EXT PDi < 0.48 ABUT<90 SINGULAR REGION
}
DIFF.c3 { @ Min. spacing of same type diff of doughnut is 0.63um(from dracula E6666)
A = INT DIFFHOLE < 0.64 ABUT<90 SINGULAR REGION
B = DIFFHOLE ENCLOSE A
AREA B < 0.3969
INT PTHOLE < 0.63 ABUT<90 SINGULAR REGION
INT NTHOLE < 0.63 ABUT<90 SINGULAR REGION
}
DIFF.c4.c5 { @ Min. spacing of opposite types diff in same well is 0.57um
@ Butting source and tap is allowed
EXT PDIFFi NTAP >0<0.57 ABUT>0<90 SINGULAR REGION INSIDE ALSO //butting is allowed
EXT NDIFFi PTAP >0<0.57 ABUT>0<90 SINGULAR REGION INSIDE ALSO //butting is allowed
}
DIFF.c6 { @ Min. spacing of opposite types diff in different well is 2.40um(dracula E1010)
// EXT PDIFF NDIFF < 2.40 ABUT<90 SINGULAR REGION INSIDE ALSO //no butting in this condition
// EXT NTAP PTAP < 2.40 ABUT<90 SINGULAR REGION INSIDE ALSO //no butting in this condition
A = DIFFi AND NWEL
B = DIFFi NOT NWEL
EXT A B <2.4 ABUT<90 SINGULAR REGION
}
DIFF.c7 { @ min area of DIFF is 0.9216
AREA DIFFi < 0.9216
}
//|------------|
//|POLY CHECKS |
//|------------|
GROUP GPOLY POLY?
POLY.d1 { @ Min. width of poly is 0.48um(NOT in sram)
A = SIZE ALLPOLY BY 0.18 OVERUNDER
INT (A NOT L46) < 0.48 ABUT<90 SINGULAR REGION
}
POLY.d1.1{ @ Min. width of poly is 0.42um(in sram area)
A = SIZE ALLPOLY BY 0.18 OVERUNDER
INT (A AND L46) < 0.42 ABUT<90 SINGULAR REGION
}
POLY.d2 { @ Min. spacing with CT between poly's on diffusion region is 1.14um
A = GT NOT INTERACT MCAP //Not include poly on MCAP
GTN = ND AND A
GTP = PD AND A
SDN = ND NOT A
SDP = PD NOT A
LTN = EXT GTN < 1.14 OPPOSITE ABUT<90 SINGULAR REGION
LTP = EXT GTP < 1.14 OPPOSITE ABUT<90 SINGULAR REGION
LTSDN = (SDN NOT L46) AND LTN
LTSDP = (SDP NOT L46) AND LTP
LTSDN INTERACT COT
LTSDP INTERACT COT
}
POLY.d3 { @ Min. spacing with no CT between poly's on diffusion region is 0.42um(reference from E13_113)
// A = EXT ALLPOLY < 0.42 ABUT<90 OPPOSITE REGION
// B = INT A < 0.04 ABUT<90 SINGULAR REGION
// C = ALLPOLY OR B
// EXT C < 0.42 ABUT<90 SINGULAR REGION
EXT ALLPOLY <0.42 ABUT<90 SINGULAR REGION
}
POLY.d4 { @ Min. spacing to diffusion is 0.03um
A = SIZE ALLPOLY BY 0.18 OVERUNDER
EXT A DIFFi < 0.03 ABUT<90 SINGULAR REGION
}
POLY.d5 { @ Min. gate lenth is 0.54um
INT GT < 0.54 ABUT<90 SINGULAR REGION
}
POLY.d7 { @ Min. Poly overlap diffusion(transistor endcap) is 0.36um
A = ENC DIFF ALLPOLY < 0.36 ABUT<90 OPPOSITE REGION
B = INT A < 0.04 ABUT<90 SINGULAR REGION
C = ENC DIFF (ALLPOLY NOT B) < 0.36 ABUT>0<90 SINGULAR REGION
C NOT IOWEL
ENC DIFF ALLPOLY < 0.04 ABUT<90 SINGULAR REGION
}
POLY.d8 { @ Min. active diffusion width is 0.57um
ENC ALLPOLY DIFF < 0.57 ABUT<90 SINGULAR REGION
}
POLY.d9 { @ Min. transistor width is 0.9um
X = ALLPOLY INSIDE EDGE DIFF
PATH LENGTH X < 0.9
}
POLY.d10 { @ Min. spacing from gate area to butted tap is 0.6um
A = COIN EDGE PD ND
B = COIN EDGE ND PD
EXT GT A < 0.6 ABUT PERPENDICULAR ALSO REGION
EXT GT B < 0.6 ABUT PERPENDICULAR ALSO REGION
}
//POLY.da { @ 90 degree gate is not allowed
// A = (GT NOT NWC) INSIDE EDGE DIFF
// INT A <0.02 ABUT==90 INTERSECTING ONLY REGION
// EXT A <0.02 ABUT==90 INTERSECTING ONLY REGION
//}
POLY.d11 { @ NCH inside NWELL is not allowed(from dracula E2222)
@ PCH outside NWELL is not allowed(from dracula E2121)
ALLPOLY AND NTAP
((ALLPOLY AND PTAP) NOT L80) NOT L51
}
POLY.da { @ 90 degree poly gate in active region is not allowed
EXT GATE_TR < 0.01 ABUT==90 INTERSECTING ONLY REGION
}
POLY.db { @ NWEL touch (ALLPOLY ENCLOSE MCAP) is prohibited
@ this rule is according to dracula E62 (cz6h.chk3)
A = ALLPOLY ENCLOSE (ALLPOLY AND MCAP)
B = A NOT NWEL
NWEL TOUCH B
}
POLY.dc { @ Nwell(Layer=31) strided Poly enclose MEC is prohibited
@ this rule is according to dracula E56 (cz6h.chk3)
A = ALLPOLY ENCLOSE (ALLPOLY AND MCAP)
B = A NOT IONW
IONW TOUCH B
}
POLY.dd { @ MEC OVERLAP NWC NWR is prohibited
@ this rule is according to dracula E35 (cz6h.chk3)
A = ALLPOLY ENCLOSE (ALLPOLY AND MCAP)
B = NWC OR NWR
A AND B
}
//|------------|
//|SCOT CHECKS|
//|------------|
GROUP GSCOT SCOT?
SCOT.e1 { @ Min. and Max. width of a SCOT region
NOT RECTANGLE SCOT == 0.48 BY == 0.48
}
SCOT.e2 { @ Min. spacing between two SCOT regions
XSCOT = SCOT NOT INTERACT MCAP
EXT XSCOT < 0.48 ABUT<90 SINGULAR REGION
}
SCOT.e3 { @ Min. spacing to diffusion is 0.36um
EXT SCOT DIFFi < 0.36 ABUT<90 SINGULAR REGION
}
SCOT.e4 { @ Min. spacing to gate area or poly on field is 0.36um
EXT SCOT ALLPOLY < 0.36 ABUT<90 SINGULAR REGION
}
SCOT.e5.e7 { @ Min. spacing of diffusion overlap SCOT on active is 0.24
@ Min. spacing of diffusion overlap SCOT on tap is 0.24
//A = PDIFF OR NTAP
//B = NDIFF OR PTAP
//ENC (SCOT AND A) A < 0.24 ABUT<90 SINGULAR REGION
//ENC (SCOT AND B) B < 0.24 ABUT<90 SINGULAR REGION
ENC (SCOT AND DIFFi) DIFFi < 0.24 ABUT<90 SINGULAR REGION
}
SCOT.e6 { @ Min. spacing of poly overlap SCOT
ENC (SCOT AND ALLPOLY) ALLPOLY < 0.3 ABUT<90 SINGULAR REGION
}
SCOT.e8.e9 { @ Min. spacing from S/D SCOT to butted tap spacing is 0.21
@ Min. spacing of butted diff tap overlap SCOT is 0.21
EXT SCOT NBUT_E < 0.21 ABUT<90 REGION
EXT SCOT PBUT_E < 0.21 ABUT<90 REGION
}
SCOT.e10 { @ floating cont is prohibited
A = (COT NOT DIFFi) NOT (ALLPOLY OR RPOLY)
A NOT L20
COT NOT ME1
}
SCOT.e11 { @ Contact on gate area is prohibited
COT AND GATE
}
//|------------|
//|LCOT CHECKS|
//|------------|
GROUP GLCOT LCOT?
LCOT.e1 { @ Long contact size is 0.48*0.96
NOT RECTANGLE LCOT == 0.48 BY == 0.96
}
LCOT.e2 { @ Min. spacing between Long Cont is 1.02
// XLCOT = LCOT NOT INTERACT MCAP
EXT LCOT < 1.02 ABUT<90 SINGULAR REGION
}
LCOT.e3 { @ Min. spacing between Long Cont and Short Cont is 1.02
EXT LCOT SCOT < 1.02 ABUT<90 SINGULAR REGION
}
LCOT.e4 { @ Min. spacing between Long Cont and Diff is 0.36
EXT LCOT DIFF < 0.36 ABUT<90 SINGULAR REGION INSIDE ALSO
}
LCOT.e5 { @ Min. spacing between Long Cont and GT is 0.66
EXT LCOT ALLPOLY < 0.66 ABUT<90 SINGULAR REGION INSIDE ALSO
}
//LCOT.e6 ong Cont only can be put in RPOLY
//|------------|
//|ME1 CHECKS |
//|------------|
GROUP GME1 ME1?
ME1.f_1 { @ Min. width of metal 1 is 0.60
INT ME1 < 0.60 ABUT<90 SINGULAR REGION
}
ME1.f_2 { @ Min. spacing between metal 1 is 0.52
A = EXT ME1 < 0.52 OPPOSITE ABUT<90 REGION
LENGTH A > 0.76
}
ME1.f_2s { @ ME1 to ME1 short run rules
EXT ME1 < 0.50 ABUT<90 REGION
}
ME1.f_3 { @ Min. spacing of ME1 overlap COT is 0.14
A = COT NOT INSIDE RPOLY //The rule of CT on RPOLY is different
ENC A ME1 < 0.14 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
ME1.f_5 { @ Min. area of ME1 is 0.774um2
AREA ME1 < 0.774
}
ME1.f_p { @ Metal-1 in the channel region of Nondope Tr. or Long-channel Tr. (L>=1um) is prohibited(from dracula EL0101,EL0102).
GT_ME1 = (GT INTERACT ME1) NOT TOUCH ME1
CHL_E = GT_ME1 COIN EDGE DIFF
CHL_E_B1 = LENGTH CHL_E >= 1
GT WITH EDGE CHL_E_B1
GT_N = GT AND VTN0
GT_N AND ME1
}
//|------------|
//|V1 CHECKS |
//|------------|
GROUP GV1 V1?
V1.g_1 { @ Size of V1 is 0.56X0.56 or 0.60X0.60
@ According to dracula E02 (chkmetal.dra.cz6h)
A = NOT RECTANGLE V1 == 0.56 BY == 0.56
NOT RECTANGLE A == 0.6 BY == 0.6
}
V1.g_2 { @ Min. spacing between V1 is 0.60um
EXT V1 < 0.60 ABUT<90 SINGULAR REGION
}
V1.g_4 { @ Min. spacing of ME1 overlap V1 is 0.14
ENC V1 ME1 < 0.14 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
//|------------|
//|ME2 CHECKS |
//|------------|
GROUP GME2 ME2?
ME2.i_1 { @ Min. width of metal 2 is 0.78
INT ME2 < 0.78 ABUT<90 SINGULAR REGION
}
ME2.i_2 { @ Min. spacing between metal 2 is 0.54
A = EXT ME2 < 0.54 OPPOSITE ABUT<90 REGION
LENGTH A > 1.00
}
ME2.i_2s { @ ME2 to ME2 short run rules
EXT ME2 < 0.46 ABUT<90 REGION
}
ME2.i_3 { @ Min. spacing of ME2 overlap V1 is 0.17
ENC V1 ME2 < 0.17 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
ME2.i_4 { @ Min. area of ME2 is 0.88um2
AREA ME2 < 0.88
}
//|------------|
//|V2 CHECKS |
//|------------|
GROUP GV2 V2?
V2.t_1 { @ Size of V2 is 0.56X0.56 or 0.60X0.60
@ According to dracula E03 (chkmetal.dra.cz6h)
A = NOT RECTANGLE V2 == 0.56 BY == 0.56
NOT RECTANGLE A == 0.6 BY == 0.6
}
V2.t_2 { @ Min. spacing between V2 is 0.60um
EXT V2 < 0.60 ABUT<90 SINGULAR REGION
}
V2.t_4 { @ Min. spacing of ME2 overlap V2 is 0.17
ENC V2 ME2 < 0.17 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
//|------------|
//|ME3 CHECKS |
//|------------|
GROUP GME3 ME3?
ME3.u_1 { @ Min. width of metal 3 is 0.78
INT ME3 < 0.78 ABUT<90 SINGULAR REGION
}
ME3.u_2 { @ Min. spacing between metal 3 is 0.54
A = EXT ME3 < 0.54 OPPOSITE ABUT<90 REGION
LENGTH A > 1.00
}
ME3.u_2s { @ ME3 to ME3 short run rules
EXT ME3 < 0.46 ABUT<90 REGION
}
ME3.u_3 { @ Min. spacing of ME3 overlap V2 is 0.17
ENC V2 ME3 < 0.17 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
ME3.u_4 { @ Min. area of ME3 is 0.88um2
AREA ME3 < 0.88
}
//|------------|
//|V3 CHECKS |
//|------------|
GROUP GV3 V3?
V3.r_1 { @ Size of V3 is 0.56X0.56
NOT RECTANGLE V3 == 0.56 BY == 0.56
}
V3.r_2 { @ Min. spacing between V3 is 0.60um
EXT V3 < 0.60 ABUT<90 SINGULAR REGION
}
V3.r_4 { @ Min. spacing of ME3 overlap V3 is 0.17
ENC V3 ME3 < 0.17 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
//|----------------------------------|
//|0.9um thickness top metal CHECKS |
//|----------------------------------|
#IFDEF TME9K
GROUP GTOPME TOPME?
TOPME.sa_1 { @ Min. width of top metal is 1
INT TOPME < 1 ABUT<90 SINGULAR REGION
}
TOPME.sa_2 { @ Min. spacing between top metal is 1
EXT TOPME < 1 ABUT<90 SINGULAR REGION
}
TOPME.sa_3 { @ Min. spacing of top metal overlap V3 is 0.22
ENC V3 TOPME < 0.22 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
TOPME.sa_4 { @ The TME9K coverage must be larger than 20% of the entire chip area
DENSITY TOPME >0< 0.20 INSIDE OF LAYER FRAME
}
TOPME.sa_5 { @ Min. area is 1um2
AREA TOPME < 1
}
#ENDIF
//|---------------------------------|
//|3um thickness top metal CHECKS |
//|---------------------------------|
#IFDEF TME30K
GROUP GTOPME TOPME?
TOPME.sb_1 { @ Min. width of top metal is 2.5
INT TOPME < 2.5 ABUT<90 SINGULAR REGION
}
TOPME.sb_2 { @ Min. spacing between top metal is 2
EXT TOPME < 2 ABUT<90 SINGULAR REGION
}
TOPME.sb_3 { @ Min. spacing of top metal overlap V3 is 0.4
ENC V3 TOPME < 0.4 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
TOPME.sb_4 { @ Min. area is 6.25um2
AREA TOPME < 6.25
}
TOPME.sb_5 { @ The TME30K coverage must be larger than 25% of the entire chip area
DENSITY TOPME >0< 0.25 INSIDE OF LAYER FRAME
}
#ENDIF
//|----------------------------------|
//|1.2um thickness top metal CHECKS |
//|----------------------------------|
#IFDEF TME12K
topmex = SIZE TOPME BY -0.16 // width > 0.32 are deleted
topmey = SIZE TOPME BY -4.83 // width >= 10 are deleted
BTOPME_b = SIZE topmey BY 4.99 // TOPME width >= 10
BTOPME_a = AND BTOPME_b TOPME
GROUP GTOPME TOPME?
TOPME.sc_1 { @ Min. width of top metal is 1.0
INT TOPME < 1.0 ABUT<90 SINGULAR REGION
}
TOPME.sc_2 { @ Min. spacing between top metal is 1
EXT TOPME < 1 ABUT<90 SINGULAR REGION
}
TOPME.sc_2w { @ Minimum spacing between metal lines with one or both metal width and length are > 10um is 1.2um
EXT BTOPME_a TOPME < 1.2 ABUT<90 SINGULAR REGION
}
TOPME.sc_3 { @ Min. spacing of top metal overlap V3 is 0.26
ENC V3 TOPME < 0.26 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
TOPME.sc_5 { @ Min. area is 1um2
AREA TOPME < 1
}
TOPME.sc_6 { @ The TME12K coverage must be larger than 25% of the entire chip area
DENSITY TOPME >0< 0.25 INSIDE OF LAYER FRAME
}
#ENDIF
//|------------|
//|NWC CHECKS |
//|------------|
GROUP GNWC NWC?
NWC.j_1 { @ Min. spacing between NWC of same potention is 1.2
EXT NWC < 1.2 ABUT<90 SINGULAR REGION CONNECTED
}
NWC.j_1s { @ Min. spacing between NWC of diffusion potention is 3.6
EXT NWC < 3.6 ABUT<90 SINGULAR NOT CONNECTED REGION
}
NWC.j_2 { @ Min. spacing between NWC and NWEL is 3.6
EXT NWC NWEL < 3.6 ABUT<90 SINGULAR REGION INSIDE ALSO
}
NWC.j_3 { @ Min. spacing between NWC and DIFF is 1.8
EXT NWC DIFFi < 1.8 ABUT<90 SINGULAR REGION
}
NWC.j_4 { @ Min. spacing of NWC overlap DIFF is 0.6
ENC (DIFF AND NWC) NWC < 0.6 ABUT<90 SINGULAR REGION
}
NWC.j_5 { @ Min. spacing between NWC and NWR is 3
EXT NWC NWR < 3 ABUT<90 SINGULAR REGION INSIDE ALSO
}
NWC.j7 { @ PD in NWC is prohibited
AND PD (NWC OR NWR)
}
//|------------|
//|NWR CHECKS |
//|------------|
GROUP GNWR NWR?
NWR.p_1 { @ Min. width of NWR is 2.4
INT NWR < 2.4 ABUT<90 SINGULAR REGION
}
NWR.p_2 { @ Min. spacing between NWR is 2.4
EXT NWR < 2.4 ABUT<90 SINGULAR REGION
}
NWR.p_3 { @ Min. spacing of NWR overlap N+ is 1.2
ENC (ND AND NWR) NWR < 1.2 ABUT<90 SINGULAR REGION
}
NWR.p_4 { @ Min. spacing to ND out of NWR is 1.2
X = DIFF NOT INSIDE NWR
EXT NWR X < 1.2 ABUT<90 SINGULAR REGION
}
NWR.p_5 { @ Min. spacing between NWR and NWEL is 3
EXT NWR NWEL < 3 ABUT<90 SINGULAR REGION INSIDE ALSO
}
NWR.p_6 { @ NWR overlap (NW or NWC or IONW) is prohibited
AND NWR ((NWEL OR NWC) OR IONW)
}
//|------------|
//|ROMC CHECKS |
//|------------|
GROUP GROMC ROMC?
ROMCGT = GT AND ROMC
ROMC.l_1 { @ Min. width of ROMC is 0.51
INT ROMC < 0.51 ABUT<90 SINGULAR REGION
}
ROMC.l_2 { @ Min. spacing between ROMC is 0.51
EXT ROMC < 0.51 ABUT<90 SINGULAR REGION
}
ROMC.l_3 { @ Min. spacing of ROMC overlap GATE is 0.21
ENC ALLPOLY ROMC < 0.21 ABUT<90 SINGULAR REGION
A = ROMC NOT ALLPOLY
NOT TOUCH ROMCGT A == 2
}
ROMC.1_4 { @ CODE overlap gate area (only allowed value 0.00)
A = ROMCGT COIN EDGE DIFF
NOT COIN EDGE A ROMC
B = ROMCGT COIN EDGE ROMC
NOT COIN EDGE B DIFF
}
ROMC.l_5 { @ Min. spacing of ROMC and GT is 0.21
EXT GT ROMC < 0.21 ABUT<90 SINGULAR REGION
}
ROMC.l_6 { @ Min. spacing of ROMC and N+ is 0.51
EXT ND ROMC <0.51 ABUT<90 SINGULAR REGION
}
ROMC.l_7 { @ Min. spacing of ROMC and NWEL is 1.8
EXT NWEL ROMC < 1.8 ABUT<90 SINGULAR REGION INSIDE ALSO
}
ROMC.l_10 { @ Min. spacing of ROMC and NWC is 1.8
EXT NWC ROMC < 1.8 ABUT<90 SINGULAR REGION INSIDE ALSO
}
ROMC.l_11 { @ Min. spacing of ROMC and NWR is 1.2
EXT NWR ROMC < 1.2 ABUT<90 SINGULAR REGION INSIDE ALSO
}
ROMC.l_12 { @ P+ diff is not allowed in ROMC area(from E1515 in dracula)
PD AND ROMC
}
ROMC.l_13 { @ VTN0,SDP is not allowed in ROMC area(from E2929 in dracula)
(VTN0 OR L57) AND ROMC
}
//|------------|
//|MCAP CHECKS |
//|------------|
GROUP GMCAP MCAP?
MCAP.q_1 { @ Min. width of MCAP is 0.66
INT MCAP < 0.66 ABUT<90 SINGULAR REGION
}
MCAP.q_2 { @ Min. spacing between MCAP is 0.66
EXT MCAP < 0.66 ABUT<90 SINGULAR REGION
}
MCAP.q_3 { @ Min. spacing between MCAP and CT is 0.66
EXT COT MCAP < 0.66 ABUT<90 SINGULAR REGION
}
MCAP.q_4 { @ Min. spacing of POLY overlap MCAP is 1.38
ENC MCAP ALLPOLY < 1.38 ABUT<90 SINGULAR REGION
}
MCAP.q_5 { @ Min. spacing of MCAP overlap CT on MCAP is 0.9
A = COT AND MCAP
ENC A MCAP < 0.9 ABUT<90 SINGULAR REGION
}
MCAP.q_6 { @ Min. spacing between MCAP and DIFF is 1.92
EXT DIFF MCAP < 1.92 ABUT<90 SINGULAR REGION INSIDE ALSO
}
MCAP.q_7 { @ Min. spacing between MCAP and NWEL is 3.24
EXT MCAP NWEL < 3.24 ABUT<90 SINGULAR REGION
}
MCAP.q_8 { @ Min. spacing between MCAP and NWC is 3.24
EXT MCAP NWC < 3.24 ABUT<90 SINGULAR REGION
}
MCAP.q_9 { @ Min. spacing between MCAP and NWR is 2.4
EXT MCAP NWR < 2.4 ABUT<90 SINGULAR REGION
}
MCAP.q_9a { @ Min. spacing between CT on the same MCAP is 9.54
AND MCAPCOT LCOT // Long COT is prohibited in MEC
A = EXT MCAPCOT < 9.54 ABUT<90 SINGULAR REGION
A INSIDE MCAP
}
MCAP.q_10 { @ Min. spacing of NWEL to POLY enclose MCAP is 0.48
A = ENCLOSE ALLPOLY MCAP
EXT A NWEL < 0.48 ABUT<90 SINGULAR REGION
}
MCAP.q_11 { @ Min. spacing of POLY(lower termal of MEC) is 0.81
A = ALLPOLY INTERACT MCAP
EXT A < 0.81 ABUT<90 SINGULAR REGION
}
MCAP.q_12 { @ Min. spacing of POLY(lower terminal of MEC) to POLY(not lower terminal) is 5.01
A = ALLPOLY INTERACT MCAP
B = ALLPOLY NOT INTERACT MCAP
EXT A B < 5.01 ABUT<90 SINGULAR REGION
}
MCAP.q_13 { @ POLY enc MEC is prohibited on DIFF
A = ENCLOSE ALLPOLY MCAP
AND A DIFF
}
MCAP.q_14 { @ Min. spacing between MCAP and IONW is 2.76
@ this rule is according to dracula E27_2 (500c.chk3)
EXT MCAP IONW < 2.76 ABUT<90 SINGULAR REGION
}
MCAP.q_a { @ 0.77 fF/um2 MIP capacitance and 1fF/um2 MIP capacitance is prohibit to use in the same design
CM = (MCAP AND ALLPOLY) NOT CAP1FF
C1 = (MCAP AND ALLPOLY) AND CAP1FF
A = (CHIP INTERACT CM) INTERACT C1
A AND (CM OR C1)
}
//|------------|
//|RPOLY CHECKS|
//|------------|
GROUP GRPOLY RPOLY?
RPOLY.v_1 { @ Min. spacing between RPOLY and DIFF is 1.02
EXT RPOLY DIFFi < 1.02 ABUT<90 SINGULAR REGION INSIDE ALSO
}
RPOLY.v_2 { @ Min. width of RPOLY is 0.81
INT RPOLY < 0.81 ABUT<90 SINGULAR REGION
}
RPOLY.v_3 { @ Min. spacing between RPOLY is 0.81
EXT RPOLY < 0.81 ABUT<90 SINGULAR REGION
}
RPOLY.v_4 { @ Min. spacing between RPOLY and POLY
EXT RPOLY ALLPOLY < 5.01 ABUT<90 SINGULAR REGION
}
RPOLY.v_6 { @ Min. spacing of RPOLY overlap CT 0.42
ENC (COT AND RPOLY) RPOLY < 0.42 ABUT<90 SINGULAR REGION
}
RPOLY.v_7 { @ CT size on RPOLY is 0.96*0.48
A = COT INSIDE RPOLY
NOT RECTANGLE A == 0.48 BY == 0.96
}
RPOLY.v_7a { @ RPOLY is prohibited on POLY,DIFF,MEC.VIA is prohibited on CT
AND RPOLY ALLPOLY
AND RPOLY DIFF
AND RPOLY MCAP
X = (V1 OR V2) OR V3
Y = COT INSIDE RPOLY
AND X Y
}
RPOLY.v_8 { @ Min. spacing of ME1 overlap CT on RPOLY is 0.3
A = COT INSIDE RPOLY
ENC A ME1 < 0.30 ABUT<90 SINGULAR REGION
}
RPOLY.v_a { @ RESID,RID2K and RID10K is prohibit to use in the same design
RL = RPOLY AND RID2K
RR = RPOLY AND RID10K
RH = RPOLY AND RESID
A = (CHIP INTERACT RL) INTERACT RR
A AND (RL OR RR)
B = (CHIP INTERACT RL) INTERACT RH
B AND (RL OR RH)
C = (CHIP INTERACT RR) INTERACT RH
C AND (RR OR RH)
}
//|------------|
//|VTN0 CHECKS|
//|------------|
GROUP GVTN0 VTN0?
VTN0.m_1 { @ Min. width of VTN0 is 0.9
INT VTN0 < 0.9 ABUT<90 SINGULAR REGION
}
VTN0.m_2 { @ Min. spacing between VTN0 is 0.48
EXT VTN0 < 0.48 ABUT<90 SINGULAR REGION
}
VTN0.m_3_4 { @ VTN0 overlap N+ DIFF is 0.00
A = ND INTERACT VTN0
NOT A VTN0
}
VTN0.m_5 { @ Min. spacing between VTN0 and DIFF is 0.57
EXT VTN0 DIFF < 0.57 ABUT<90 SINGULAR REGION
}
VTN0.m_6 { @ Min. spacing between VTN0 and NWEL is 2.28
EXT VTN0 NWEL < 2.28 ABUT<90 SINGULAR REGION
}
VTN0.m_7 { @ Min. Transistor length in VTN0 is 2.4
A = GT INTERACT VTN0
B = INSIDE EDGE A DIFF
INT B < 2.4 ABUT<90 REGION
}
VTN0.m_9 { @ Min. spacing between ND on VTN0 is 1.02
A = ND INTERACT VTN0
EXT A < 1.02 ABUT<90 SINGULAR REGION
}
VTN0.m_10 { @ Min. spacing between ND and PD on VTN0 is 0.69
A = ND AND VTN0
B = PD AND VTN0
EXT A B < 0.69 ABUT<90 SINGULAR REGION
}
VTN0.m_11 { @ Min. spacing between VTN0 and NWC is 2.28
EXT VTN0 NWC < 2.28 ABUT<90 SINGULAR REGION
}
VTN0.m_12 { @ Min. spacing between VTN0 and NWR is 1.68
EXT VTN0 NWR < 1.68 ABUT<90 SINGULAR REGION
}
VTN0.m13 { @ Min. spacing between VTN0 and IONW is 1.68(chk2 E20_220)
EXT VTN0 IONW <1.68 ABUT<90 SINGULAR REGION
}
VTN0.m14 { @ PCH Tr. in VTN0 is prohibited(chk2 E18_218)
PGATE_TR AND VTN0
}
VTN0.m15 { @ NWEL/NWC/NWR/IONW overlap VTN0 is not allowed(chk2 E18_318)
A = VTN0 NOT IOPW
B = ((NWEL OR NWC) OR NWR) OR IONW
B AND A
}
VTN0.m_a { @ VTN0 can not overlap DNW
VTN0 AND DNWX
}
//|------------------|
//|DNW rules CHECKS |
//|------------------|
DNW.aa_1 { @ DNW width is 3
INT DNWX < 3 ABUT<90 SINGULAR REGION
}
DNW.aa_2 { @ DNW space is 5
EXT DNWX < 5 ABUT<90 SINGULAR REGION
}
DNW.aa_3 { @ Minimum extension of NW beyond DNW is 0.9
ENC DNWX NWEL < 0.9 ABUT<90 SINGULAR REGION
}
DNW.aa_4 { @ Minimum overlap of NW onto DNW is 1.4
INT DNWX NWEL < 1.4 ABUT<90 SINGULAR REGION
}
DNW.aa_5 { @ Minimum clearance from DNW to NW is 4.1
EXT DNWX NWEL < 4.1 ABUT<90 SINGULAR REGION MEASURE ALL
}
//DNW.aa_6:Minimum clearance from NW edge to a N+ Active region is outside NW is 1.8
//checked by NW.a7
DNW.aa_7 { @ Minimum clearance from DNW edge to a N+ Active region is outside a NW connected to DNW is 3.0
A = (NWEL OR NWR) OR NWC
EXT DNWX (ND NOT A) < 3.0 ABUT<90 SINGULAR REGION
}
DNW.aa_a { @ DNW should be surrounded by NW
DNWX NOT INSIDE EDGE NWEL
}
DNW.aa_d { @ DNW is prohibited in NW, NWC, NWRES, VTN0
DNWX INSIDE NWEL
DNWX AND NWC
DNWX AND NWR
DNWX AND VTN0
}
//|----------------------|
//| DVTN rules check |
//|----------------------|
DVTN_ND = ND AND DVTN
DVTN.dd_1 { @ DVTN width is 0.8
INT DVTN < 0.8 ABUT<90 SINGULAR REGION
}
DVTN.dd_2 { @ DVTN space is 0.7
EXT DVTN < 0.7 ABUT<90 SINGULAR REGION
}
DVTN.dd_3 { @ Min. extension of N+ Active is 0.7
A = ND INSIDE EDGE ALLPOLY
ENC A DVTN < 0.7 ABUT<90 REGION
}
DVTN.dd_4 { @ Min. extension of Gate region(in channel length direction) is 0.7
A = ALLPOLY INSIDE EDGE ND
ENC A DVTN < 0.7 ABUT<90 REGION
}
DVTN.dd_5 { @ Min. clearance to other Gate region is 0.7
EXT DVTN GATE < 0.7 ABUT<90 SINGULAR REGION
}
DVTN.dd_6 { @ Min. clearance to N+/P+ Active is 0.7
EXT DVTN DIFF < 0.7 ABUT<90 SINGULAR REGION
}
DVTN.dd_7 { @ Channel length(fixed) is 10.0
DVPO_E = ALLPOLY INSIDE EDGE DVTN_ND
INT DVPO_E < 10 ABUT<90 REGION
A = EXPAND EDGE DVPO_E INSIDE BY 5
B = ALLPOLY AND DVTN_ND
B NOT A
}
DVTN.dd_8 { @ Min. Channel width is 2
A = DVTN_ND INSIDE EDGE ALLPOLY
INT A < 2 ABUT<90 REGION
}
DVTN.dd { @DVTN can't overlap P+ Active
DVTN AND PD
}
//|-----------------|
//| POLY FUSE check |
//|-----------------|
FUSE = POLY AND FUSEID
FUSE_W = FUSE COIN EDGE FUSEID
FUSE_L = FUSE INSIDE EDGE FUSEID
FUSE_L_EXT = EXPAND EDGE FUSE_L BY FACTOR 6
FUSE_EXT = SIZE FUSE_L_EXT BY 2
// FUSID_EXT = SIZE FUSEID BY 2
FUSE_T = (POLY INTERACT FUSEID) NOT FUSE_EXT
FUSE.u1 { @ Fuse length (Fixed) is 2.0
LENGTH FUSE_L < 2.0
NOT AREA FUSE ==1.1
}
FUSE.u2 { @ Fuse width (fixed) is 0.55
INT FUSE < 0.55 ABUT<90 SINGULAR REGION
SIZE FUSE BY 0.275 UNDEROVER
}
FUSE.u3.u4 { @ Electrode width (Fixed) is 12
NOT RECTANGLE FUSE_T == 12 BY == 12
}
//FUSE.u5 checked by FUSE.u3.u4
//|--------------------------|
//| ESD NMOS rules check |
//|--------------------------|
ESDN = (ND AND IOID) INTERACT SB
ESDN_GATE_W = ALLPOLY INSIDE EDGE ESDN
ESDN_GATE = ALLPOLY AND ESDN
ESDN_POLY = ALLPOLY INTERACT ESDN_GATE
ESDN_S = (ESDN NOT POLY) NOT INTERACT SB
ESDN_D = (ESDN NOT POLY) INTERACT SB
CT_S = COT AND ESDN_S
CT_D = COT AND ESDN_D
ND_IN_PO = ESDN INSIDE EDGE ALLPOLY
ESDN_X = ESDN TOUCH EDGE ND_IN_PO
ESDN.w1 { @ Single finger width for ESD Nch Buffer and Pch Buffer 25~50
PATH LENGTH ESDN_GATE_W < 25
PATH LENGTH ESDN_GATE_W > 50
}
ESDN.l1 { @ Gate Length of Nch Buffer (5V) is 0.6(fixed)
INT ESDN_GATE < 0.6 ABUT<90 SINGULAR REGION
SIZE ESDN_GATE BY 0.3 UNDEROVER
}
ESDN.A { @ Min Clearance from SB to Poly on drain side of NMOS is 3.68
ENC ESDN_GATE_W SB < 3.68 ABUT<90 REGION
}
ESDN.B { @ SB overlap Poly on drain is 0.3(fixed)
INT SB ESDN_GATE < 0.3 ABUT<90 SINGULAR REGION
A = SB AND ESDN_GATE
SIZE A BY 0.15 UNDEROVER
}
ESDN.C { @ Min SB to Contact space is 0.5
EXT SB CT_D < 0.5 ABUT<90 SINGULAR REGION
}
ESDN.D { @ Min SB overlap drain diffusion is 1.72
INT ESDN_X SB < 1.72 ABUT<90 REGION
}
ESDN.E { @ Min SB clearance to Diffusion is 0.5
ENC ESDN_X SB < 0.5 ABUT<90 REGION
}
ESDN.F { @ Min Contact to Gate space on source is 0.57
EXT ESDN_POLY CT_S < 0.57 ABUT<90 SINGULAR REGION
}
ESDN.G { @ Min Ndiff extension to Contact on source is 0.75
ENC CT_S ESDN < 0.75 ABUT<90 SINGULAR REGION
}
ESDN.H { @ Min Ndiff to Pdiff Pickup space is 3.71
EXT ESDN PD < 3.71 ABUT<90 SINGULAR REGION
}
//|------------|
//|DEN CHECKS |
//|------------|
GROUP GPD PD?
PD.ME1 {@ Minimum M1 pattern density is 20%
DENSITY ME1 >0< 0.2 INSIDE OF LAYER FRAME
}
PD.ME2 {@ Minimum M2 pattern density is 20%
DENSITY ME2 >0< 0.2 INSIDE OF LAYER FRAME
}
PD.ME3 {@ Minimum M3 pattern density is 20%
DENSITY ME3 >0< 0.2 INSIDE OF LAYER FRAME
}
PD.additional {@ chip not covered by FRAME
CHIP NOT FRAME
}
//|------------|
//|Pch CHECKS|
//|------------|
GROUP GPch Pch?
Pch.A.C {@Min gate lenth is 0.78(Fixed)
INT PBGT < 0.78 ABUT<90 SINGULAR REGION
SIZE PBGT BY 0.39 UNDEROVER
}
Pch.K {@Min gate width is 25.2um
A = INSIDE EDGE PBPF ALLPOLY
INT A < 25.2 ABUT<90 REGION
}
Pch.E {@Gate poly edge to Drain cot edge spacing is 3.06~4.56
EXT PBDCT PBGT < 3.06 ABUT<90 SINGULAR REGION
A = SIZE PBGT BY 4.56
PBDCT NOT INTERACT A
}
Pch.F {@Gate poly edge to Source cot edge spacing is 0.57~1.8
EXT PBSCT PBGT < 0.57 ABUT<90 SINGULAR REGION
A = SIZE PBSPC BY 1.8
B = SIZE (PBSCT NOT PBSPC) BY 1.8
PBSPC inside (A NOT INTERACT PBGT)
PBSCT inside (B NOT INTERACT PBGT == 2)
}
Pch.G.H {@Diff overlap Source or Drain contact in parallel to gate is 3.36
@Diff overlap Source or Drain contact in perpendicular to gate is 0.84
ENC PBSDCT PBPF_PERP < 0.84 ABUT<90 REGION
ENC PBSDCT PBPF_PARA < 3.36 ABUT<90 REGION
}
Pch.I {@Guard ring diff to source drain diff spacing is 3.96(fixed)
A = PBPF SIZE BY 3.96
B = NOT COIN EDGE A PBNF
EXPAND EDGE B INSIDE BY 3.96
}
Pch.J {@Min width of guard ring diff is 2.16
INT PBNF < 2.16 ABUT<90 SINGULAR REGION
}
/*
Pch.L {@Min width of guard ring metal
A = ME1 INTERACT PBNFCT
B = ME2 INTERACT PBNFCT
C = ME3 INTERACT PBNFCT
INT A < 2.16 ABUT<90 SINGULAR REGION
INT B < 2.16 ABUT<90 SINGULAR REGION
INT C < 2.16 ABUT<90 SINGULAR REGION
}
*/
//|------------|
//|Nch CHECKS|
//|------------|
GROUP GNch Nch?
Nch.A {@Min gate lenth is 0.81(Fixed)
A = NBFS AND NBPOLY
NBGT = A NOT NBNW
INT NBGT < 0.81 ABUT<90 SINGULAR REGION
SIZE NBGT BY 0.405 UNDEROVER
}
Nch.E {@Width of gate poly is 1.65(FIXED)
// B = NBNW AND ND
// E1 = INT NBPOLY < 1.65 ABUT<90 OPPOSITE SINGULAR REGION
// E = SIZE NBPOLY BY -0.825
// E2 = SIZE E BY 0.825
// E1 AND B
// E2 AND B
A = SIZE NBNF BY 0.3 OVERUNDER
B = A AND NBPOLY
INT B < 1.65 ABUT<90 OPPOSITE SINGULAR REGION
SIZE B BY 0.825 UNDEROVER
}
Nch.F {@Source diff overlap nwel is 0.6(Fixed)
A = NBFS AND NBNW
INT A < 0.6 ABUT<90 SINGULAR REGION
SIZE A BY 0.3 UNDEROVER
}
Nch.G {@Min Spacing between gate poly edge and source edge is 0.24(fixed)
ENC NBFS NBPOLY < 0.24 ABUT<90 SINGULAR REGION
A = SIZE NBFS BY 0.24
B = A AND NBPOLY
C = NBPOLY NOT B
INT C < 0.12 ABUT<90 SINGULAR REGION
D = TOUCH B C >1<3
B NOT D
}
Nch.H {@Drain diff edge to Drain contact in perpendicular to gate is 1.02(fixed)
A = SIZE NBFD BY -1.02
B = NBFD NOT A
C = COIN EDGE NBFDCOT B
NBFDCOT NOT WITH EDGE C == 2
}
Nch.I {@Diff overlap source or drain cot in direction parallel to the gate is 3.36
// NBFD_S = SIZE NBFD BY -1.03
// ENC NBFDCOT NBFD_S < 2.33 ABUT<90 SINGULAR REGION
// NBPOLY_S = SIZE NBPOLY BY 1.04
// NBPNS = NBPOLY_S AND NBFS
// A = ENC NBFSCOT NBPNS < 3.36 OPPOSITE REGION
// INTERACT A POLY
S_D = NBFD OR NBFS
S_D_E = SIZE S_D BY 0.3 OVERUNDER
ENC NBFDCOT S_D_E < 3.36 ABUT<90 REGION
NBFS_X = (NBFS NOT IONW) NOT TOUCH EDGE IONW
NBFS_X_E = NBFS_X INSIDE EDGE NBPOLY
NBFS_X_EE = NBFS_X TOUCH EDGE NBFS_X_E
ENC NBFSCOT NBFS_X_EE < 3.36 ABUT<90 REGION
}
Nch.J {@Gate edge to source cot edge sapcing is 0.57(fixed)
// EXT NBPOLY NBFSCOT < 0.57 ABUT<90 SINGULAR REGION
// NBPOLY_S = SIZE NBPOLY BY 0.57
// NOT TOUCH NBFSCOT NBPOLY_S
NBFSCOT_1 = SIZE NBFSCOT BY 1.98 OVERUNDER
SOR_T_PO_E = NBPOLY INSIDE EDGE NBFS
SOR_T_PO_E_EX = EXPAND EDGE SOR_T_PO_E OUTSIDE BY 0.57
// NBPOLY_S = NBPOLY AND NBFS
// NBFS_S = NBFS INTERACT NBPOLY_S == 1
// CT_IN_NBFS_S = NBFSCOT INSIDE NBFS_S
// NBFS_T = NBFS INTERACT NBPOLY_S == 2
// CT_IN_NBFS_T = NBFSCOT INSIDE NBFS_T
// CT_IN_NBFS_S NOT TOUCH SOR_T_PO_E_EX == 1
// CT_IN_NBFS_T NOT TOUCH SOR_T_PO_E_EX == 2
SOR_T_PO_E_EX NOT TOUCH NBFSCOT_1
}
Nch.K {@Diff overlap source cot edge spacing in the direct perpendicular to the gate is 0.78
ENC NBFSCOT NBFS < 0.78 ABUT<90 SINGULAR REGION
}
Nch.L {@Source diff edge to drain diff edge spacing is 0.60(fixed)
// EXT NBFS NBFD < 0.60 ABUT<90 SINGULAR REGION
A = SIZE NBFD BY 0.60
A NOT TOUCH NBFS == 2
}
Nch.M {@Guard ring diff width is 2.16
INT NBPF < 2.16 ABUT<90 SINGULAR REGION
}
/*
Nch.N {@Guard ring metal width is 2.16
A = ME1 INTERACT NBPFCOT
B = ME2 INTERACT NBPFCOT
C = ME3 INTERACT NBPFCOT
INT A < 2.16 ABUT<90 SINGULAR REGION
INT B < 2.16 ABUT<90 SINGULAR REGION
INT C < 2.16 ABUT<90 SINGULAR REGION
}
*/
Nch.O {@Tr diff edge to guard ring diff spacing is 3.96(fixed)
// EXT NBPF NBNF < 3.96 ABUT<90 SINGULAR REGION
// A = SIZE NBNF BY 3.96
// B = A NOT NBNF
// C = HOLES (NBNF OR NBPF)
// D = C NOT B
// ENCLOSE B D
EXT NBPF NBNF < 3.96 ABUT<90 SINGULAR REGION
A = SIZE NBNF BY 3.97
B = A AND NBPF
A NOT ENCLOSE B
}
Nch.P {@Tr nwel edge to guard ring diff spacing is 2.94(fixed)
// EXT NBNW PD < 2.94 ABUT<90 SINGULAR REGION
// A = HOLES PD
// B = SIZE A BY -2.94
// C = NOT A B
// D = TOUCH NBNW C
// NBNW NOT D
A = NBNW INSIDE EDGE NBFS
B = NBNW NOT TOUCH EDGE A
C = EXPAND EDGE B OUTSIDE BY 2.94
C NOT TOUCH PD
}
Nch.Q {@Min gate width is 25.2um
A = SIZE NBFS BY 0.25
B = A INSIDE EDGE NBPOLY
INT B < 25.7 ABUT<90 REGION
}
Nch.R {@Min NBUF endcap is 0.36
A = ENC NBFS NBPOLY < 0.36 ABUT<90 OPPOSITE REGION
A NOT INSIDE IOWEL
}
Nch.S {@Min IONW overlap diff is 1.02(from dracula E04104)
A101 = NWD ENCLOSE (IONW AND L79)
NW_D = NWD WITH TEXT "U%%NDIODE"
NW_C = NWD NOT ((L51 OR L52) OR L80)
ENC DIFF ((NW_C NOT A101) NOT NW_D) < 1.02 ABUT<90 SINGULAR REGION
}
Nch.AA {@IONW/IOPW for Nch buffer must be complete coinsident (According to dracula EN22)
A = IOPW ENCLOSE NBNW
B = IONW ENCLOSE NBNW
XOR A B
}
//|----------------------------------------------------|
//| Connected VCC,GND Pch,Nch transistor spacing check |
//|----------------------------------------------------|
VIRTUAL CONNECT NAME "?VDD?" "?VCC?" "?VPP?" "?VSS?" "?GND?"
LVS POWER NAME "?VDD?" "?VCC?"
LVS GROUND NAME "?VPP?" "?VSS?" "?GND?"
PME1 = ME1 NET "?VDD?" "?VPP?" "?VCC?"
PCOT = COT INSIDE PME1
GME1 = ME1 NET "?GND?" "?VSS?"
GCOT = COT INSIDE GME1
NBUD = NDIFF INSIDE IOWEL
NBUS = NDIFF CUT IOWEL
NBUF = NBUD OR NBUS
NTRSDV = NTRV NOT IOWEL
NBUFV = NTRV AND IOWEL
HNBUFB = IOWEL ENCLOSE NBUFV
TMP02 = L80 AND HNBUFB
TMP03 = HNBUFB ENCLOSE TMP02
HNBUF = HNBUFB NOT TMP03
TMP002 = SIZE (PD NOT ALLPOLY) BY 0.01
NPCON = TMP002 AND (ND NOT ALLPOLY)
PDIFF_1 = (PD NOT ALLPOLY) OR NPCON
PDIFFT = PDIFF_1 AND NWEL
NDIFFT = (ND NOT ALLPOLY) NOT NWEL
NTRV = (NDIFFT NOT ALLPOLY) ENCLOSE PCOT
PTRSDV = (PDIFFT NOT ALLPOLY) ENCLOSE PCOT
NTRSDG = (NDIFFT NOT ALLPOLY) ENCLOSE GCOT
PTRSDG = (PDIFFT NOT ALLPOLY) ENCLOSE GCOT
Vg.A {@ Min. NDIFF CONNECTED GROUND TO NWELL CONNECTED POWER is 3.51
TMP1 = NTRSDG NOT NBUS
A= EXT HNBUF TMP1 < 3.51 ABUT<90 SINGULAR REGION
B= EXT HNBUF TMP1 < 3.51 OPPOSITE ABUT<90 SINGULAR REGION
C = B INSIDE ALLPOLY
A NOT INTERACT C
}
Vg.B {@ Min. PDIFF CONNECTED POWER TO PDIFF CONNECTED GROUND is 3.51
A = EXT PTRSDV PTRSDG < 3.51 ABUT<90 SINGULAR REGION
A NOT INSIDE PDi
}
//|------------|
//|DIO CHECKS|
//|------------|
GROUP GDIO DIO?
NNDI = ND ENCLOSE DNW //DIODE N DIFF
//A = SIZE NNDI BY -1.282
//NNDIODE = SIZE A BY 1.282
NNDIODE = EXTENTS NNDI
DIO.1 { @ Min width of DNW is 1.2
INT DNW < 1.2 ABUT<90 SINGULAR REGION
A = IONW INTERACT DNW
B = IOPW INTERACT DNW
XOR A B
}
DIO.2 { @ NDDI overlap DNW is 0.96
A = SIZE DNW BY 0.96
XOR A NNDIODE
}
DIO.3 {@Beveled DIFF layer is 0.75
A = NNDIODE NOT NNDI
ANGLE A >0 <45
ANGLE A >45 <90
// A_45 = ANGLE A == 45
A_90 = NOT ANGLE A == 45
NOT LENGTH A_90 == 0.75
}
DIO.4 {@Guard ring to NDI spacing is 3.96
// EXT NNDIODE PD < 3.96 ABUT<90 SINGULAR REGION
// A = HOLES PD
// B = A ENCLOSE NNDIODE
// C = SIZE NNDIODE BY 3.96
// NOT C B
// NOT B C
A = HOLES PD INNER EMPTY
B = A ENCLOSE NNDIODE
C = SIZE NNDIODE BY 3.96
XOR B C
}
DIO.5 {@Guard ring width is 2.16
A = HOLES PD INNER
B = A ENCLOSE NNDIODE
C = TOUCH PD B
INT C < 2.16 ABUT<90 SINGULAR REGION
}
DIO.6 {@According to dracula ED06_1
DOD13 = NNDI AND IOPW
DOD13A = IOPW ENCLOSE DOD13
DOD31 = NNDI AND IONW
DOD31A = IONW ENCLOSE DOD31
XOR DOD31A DOD13A
}
/*
DIO.7 {@According to darcula ED06_2
DIO35 = ND AND X35
D13A = IOPW AND DIO35
D31A = IONW AND DIO35
XOR D31A D13A
}
*/
//|------------------------------|
//| design rules for guard ring |
//|------------------------------|
NW_IO = NWEL AND IOID
NW_GR = NWEL AND GRID
NW_IN = NWEL NOT (IOID OR GRID)
ND_IO = ND AND IOID
PD_IO = PD AND IOID
ND_GR = ND AND GRID
PD_GR = PD AND GRID
GRD = ND_GR OR PD_GR
DIFF_GR = ND_GR OR PD_GR
M1_GR = ME1 AND GRID
M2_GR = ME2 AND GRID
M3_GR = ME3 AND GRID
NACT_IO = ND_IO NOT NWEL
NACT_IN = NDIFF NOT IOID
PACT_IO = PD_IO AND NWEL
PGT_IO = GT AND PACT_IO
Latchup.A {@ Minimum spacing from N-well in I/O area to N+ Diffusion in core area is 32.4
@ Minimum spacing from N+ Diffusion in I/O area to N-well in core area is 32.4
A = NW_IO ENCLOSE PGT_IO
B = NW_IN ENCLOSE PGT
EXT A NACT_IN < 32.4 ABUT<90 SINGULAR REGION
EXT NACT_IO B < 32.4 ABUT<90 SINGULAR REGION
}
Latchup.B {@ Minimum spacing from N-well in core area to N-well in guard ring 16.8
EXT NW_IN NW_GR < 16.8 ABUT<90 SINGULAR REGION
}
Latchup.C {@ Min. spacing from N-well in guard ring to active, metal-1,metal-2, and metal-3 in guard ring is 0.6
ENC ND_GR NW_GR < 0.6 ABUT<90 SINGULAR REGION
ENC M1_GR NW_GR < 0.6 ABUT>0<90 SINGULAR REGION
ENC M2_GR NW_GR < 0.6 ABUT>0<90 SINGULAR REGION
ENC M3_GR NW_GR < 0.6 ABUT>0<90 SINGULAR REGION
}
Latchup.D {@ Min. width of guardring is 3
INT ND_GR < 3 ABUT<90 SINGULAR REGION
INT PD_GR < 3 ABUT<90 SINGULAR REGION
}
Latchup.E {@ Minimum spacing from N-well in guard ring to P+ diffusion in guard ring 1.8
EXT NW_GR PD_GR < 1.8 ABUT<90 SINGULAR REGION
}
Latchup.F {@ Minimum spacing from metal-1 in guard ring to matal-1 which crosses the guard ring area is 0.54
M1_GR_C = ME1 CUT GRID
A = EXT M1_GR_C M1_GR < 0.54 ABUT<90 SINGULAR REGION
A AND GRD
}
Latchup.G {@ Minimum spacing from active in guard ring to poly which crosses the guard ring area is 0.06
POLY_C_G = ALLPOLY CUT GRID
A = EXT POLY_C_G DIFF_GR < 0.06 ABUT<90 SINGULAR REGION
A AND GRID
}
Latchup.H {@ Minimum spacing from N-well in I/O area to N+Diffusion in I/O area is 32.4
A = NW_IO ENCLOSE PGT_IO
EXT A NACT_IO < 32.4 ABUT<90 SINGULAR REGION
}
Nwell_VDD = NWEL NET "?VDD?" "?VPP?" "?VCC?"
Pdiff_VDD = PSD NET "?VDD?" "?VPP?" "?VCC?"
Nwell_GND = NWEL NET "?GND?" "?VSS?"
Latchup.I {@ Minimun spacing from VDD connected N-Well and GND connected N-Well is 23.04
A = Nwell_VDD ENCLOSE Pdiff_VDD
EXT A Nwell_GND < 23.04 ABUT<90 SINGULAR REGION
}
//|--------------------|
//| SLOT rule checks |
//|--------------------|
TOPME_SLOT = (HOLES TOPME INNER) AND SLTID
SLOT_TOPME = TOPME OR TOPME_SLOT
SLOT.L.W {@ SLOT length is 120,SLOT width is 2
NOT RECTANGLE TOPME_SLOT == 120 BY == 2
}
SLOT.S {@ Min slot space is 9.6
EXT TOPME_SLOT < 9.6 ABUT<90 SINGULAR REGION
}
SLOT.E {@ Min metal overlap slit is 9.6
ENC TOPME_SLOT SLOT_TOPME < 9.6 ABUT<90 SINGULAR REGION
}
//|--------------------|
//| Pad rule checks |
//---------------------|
PAD.1 { @metal overlap cover is 4.02
ENC COVER ME1 < 4.02 ABUT<90 SINGULAR REGION
ENC COVER ME2 < 4.02 ABUT<90 SINGULAR REGION
ENC COVER ME3 < 4.02 ABUT<90 SINGULAR REGION
ENC COVER TOPME < 4.02 ABUT<90 SINGULAR REGION OUTSIDE ALSO
}
//|-------------------|
//| OBS Rule checks |
//|-------------------|
OBS.ME1 {@ Min OBS to ME1 space is 0.52
EXT ME_OBS ME1 < 0.52 ABUT>0<90 SINGULAR REGION
}
OBS.ME2 {@ Min OBS to ME2 space is 0.54
EXT ME_OBS ME2 < 0.54 ABUT>0<90 SINGULAR REGION
}
OBS.ME3 {@ Min OBS to ME3 space is 0.54
EXT ME_OBS ME3 < 0.54 ABUT>0<90 SINGULAR REGION
}
OBS.DIFF {@ Min OBS to diff space is 2.4
EXT ME_OBS DIFF < 2.4 ABUT>0<90 SINGULAR REGION
}
OBS.POLY {@ Min OBS to poly space is 1.14
EXT ME_OBS ALLPOLY < 1.14 ABUT>0<90 SINGULAR REGION
}
OBS.NWEL {@ Min OBS to NWELL space is 3.6
EXT ME_OBS ALLNW < 3.6 ABUT>0<90 SINGULAR REGION
}
//|-----------------|
//|IONW/IOPW checks |
//|-----------------|
IO.h.1 {@ spacing of IONW is 1.8(same potential)
EXT IONW < 1.8 ABUT<90 SINGULAR REGION CONNECTED
}
IO.h.2 {@ spacing of IONW is 2.4(different potential)
EXT IONW < 2.4 ABUT<90 SINGULAR REGION NOT CONNECTED
}
IO.h.3 {@ NWR to IONW spacing is 2.4
EXT NWR IONW < 2.4 ABUT<90 SINGULAR REGION INSIDE ALSO
}
IO.h.4 {@ CODE to IONW spacing is 1.2
EXT ROMC IONW < 1.2 ABUT<90 SINGULAR REGION INSIDE ALSO
}
IO.h.5 {@ NWC to IONW spacing is 3.0
EXT NWC IONW < 3 ABUT<90 SINGULAR REGION INSIDE ALSO
}
IO.h.6 {@ Spacing to N+/P+ diffusion out of IONW is 1.2(from dracula E05105)
X = IONW NOT ((L51 OR L52) OR L80)
EXT DIFF X < 1.2 ABUT<90 SINGULAR REGION
}
IO.h.a {@ PROHIBITE PROHIBITE OVERLAP NWELL AND NWELL(ACCSR) (from dracula E6262)
IONW AND NWEL
}
IO.hb { @ NWELL(ACCESSORY=ACCSR) WIDTH 2.4 (from dracula chk1 E02_202
A = ((IONW NOT L80) NOT L52) NOT L51
B = A NOT DNW
INT B <2.4 ABUT<90 SINGULAR REGION
}
#IFDEF IN_USE
//|------------|
//|RNW CHECKS |
//|------------|
/////////////////////////////////////////
//According to dracula rules ER01~ER05///
/////////////////////////////////////////
RNWCOT = RNW AND ( COT AND ND )
RNW.p1_1 { @ Min NWR WIDTH is 2.4
INT RNW < 2.4 ABUT<90 SINGULAR REGION
}
RNW.p1_2 { @ Min space between NWR and PD
EXT RNW PD < 3.96 ABUT<90 SINGULAR REGION
}
RNW.p1_3 { @ according dracula rule ER03, NWELL RESI OVERLAP CONTACT ON TAP
ENC RNWCOT RNW < 3.36 ABUT<90 SINGULAR REGION
}
RNW.p1_4 { @ according dracula rule ER04,NWELL RESI METAL 1 OVERLAP CONTACT ON TAP
ENC RNWCOT ME1 <2.52 ABUT<90 SINGULAR REGION
}
RNW.p1_5 { @ according dracula rule ER05,Min POLY RESI WIDTH is 0.72
INT POLYRR < 0.72 ABUT<90 SINGULAR REGION
}
//|------------|
//|FDN CHECKS|
//|------------|
GROUP GFDN FDN?
NND = ND AND VTN0
NNDD = ND INSIDE NNDNW
NNDS = NND CUT NNDNW
NNDG = NNDS AND ALLPOLY
NNDPOLY = ALLPOLY ENCLOSE NNDG
NNDPS = NNDPOLY AND NNDS
NNDL = NNDPS NOT NNDNW
NNDSD = NNDD OR NNDS
NNDSD_SIZ = SIZE NNDSD BY 0.3
NNDSDD = SIZE NNDSD_SIZ BY -0.3
NNDSCON = NNDS AND COT
NNDS02 = NNDS AND ND
NNDS38 = NNDS AND VTN0
NNDS02T = ND ENCLOSE NNDS02
NNDS38T = VTN0 ENCLOSE NNDS38
NNDS_SIZ = SIZE NNDS BY 0.24
NNDPOLY_N_NNDS = NNDPOLY NOT NNDS_SIZ
NNDPOLY_A_NNDS = NNDPOLY AND NNDS_SIZ
NNDPOLY_TMP1 = NNDPOLY_A_NNDS TOUCH NNDPOLY_N_NNDS == 2
NNDS_NNNDG = NNDS NOT NNDG
NNDS1 = NNDS_NNNDG TOUCH NNDG == 1
NNDS2 = NNDS_NNNDG TOUCH NNDG == 2
NNDSC1 = NNDS1 AND NNDSCON
NNDSC2 = NNDS2 AND NNDSCON
NNDG_SIZ = SIZE NNDG BY 0.57
NNDSD_399 = SIZE NNDSD BY 3.99
NNDSD_399PD = NNDSD_399 AND PD
NNDDM = NNDSD_399 NOT PD
NNDPF = PD ENCLOSE NNDSD_399PD
NNDD15 = SIZE NNDD BY 0.36
NNDD15T = NNDD15 TOUCH NNDPOLY
NNDDCON = NNDD AND COT
FDN.1 {@ According to EO01_1
A = NNDS AND NNDNW
INT A < 0.6 ABUT >0<90 SINGULAR REGION
}
FDN.2 {@According to EO01_2
NNDPS_S = SIZE NNDPS BY -0.3
SIZE NNDPS_S BY 0.3
}
FDN.3 {@According to EO02_1
ENC NNDS NNDPOLY < 0.24 ABUT<90 SINGULAR
}
FDN.4 {@According to EO02_2
NNDPOLY_A_NNDS NOT NNDPOLY_TMP1
}
FDN.5 {@According to EO03_1
ENC NNDDCON NNDD < 1.02 ABUT<90 SINGULAR REGION
}
FDN.6 {@According to EO03_2
TMP1 = SIZE NNDD BY -1.022
TMP2 = NNDDCON NOT TMP1
TMP3 = NNDDCON AND TMP1
TMP4 = TMP3 TOUCH TMP2 == 2
TMP3 NOT TMP4
}
FDN.7 {@According to EO04_1
EXT NNDSCON NNDPOLY < 0.57 ABUT<90 SINGULAR REGION
}
FDN.8 {@According to EO04_2
A = NNDSC1 TOUCH NNDG_SIZ == 1
NOT NNDSC1 A
}
FDN.9 {@According to EO04_3
A = NNDSC2 TOUCH NNDG_SIZ ==2
NOT NNDSC2 A
}
FDN.10 {@According to EO05
ENC NNDSCON NNDS < 0.78 ABUT<90 SINGULAR REGION
}
FDN.11 {@According to EO06
INT NNDPF < 2.16 ABUT<90 SINGULAR REGION
}
FDN.12 {@According to EO07_1
EXT NNDS PD < 3.96 ABUT<90 SINGULAR REGION
}
FDN.13 {@According to EO07_2
EXT NNDD PD < 3.96 ABUT<90 SINGULAR REGION
}
FDN.14 {@According to EO07_3
A = HOLES NNDSD_399PD
B = A NOT NNDSD_399PD
C = B INSIDE NNDDM
D = NNDDM INSIDE C
NNDDM NOT D
}
FDN.15 {@According to EO08_1
EXT NNDNW PD < 2.94 ABUT<90 SINGULAR REGION
}
FDN.16 {@According to EO08_2
A = SIZE NNDPF BY 2.97
B1 = NNDNW AND A
B2 = NNDNW NOT A
C = B2 TOUCH B1 == 2
NOT B2 C
}
FDN.17 {@According to EO09;ENDCAP
ENC NNDSDD NNDPOLY < 0.36 ABUT<90 SINGULAR REGION
}
FDN.18 {@According to EO10_1;NW OVER FD
ENC NNDSDD NNDNW < 1.02 ABUT<90 SINGULAR REGION
}
FDN.19 {@According to EO10_2
A = SIZE NNDSDD BY 1.02
NNDNW NOT A
}
FDN.20 {@According to EO11
A = IOPW ENCLOSE NNDNW
B = IONW ENCLOSE NNDNW
XOR A B
}
FDN.21 {@According to EO12_1 ; FD-PO
EXT NNDD NNDPOLY < 0.36 ABUT<90 SINGULAR REGION
}
FDN.22 {@According to EO12_2
NOT NNDD15 NNDD15T
}
FDN.23 {@According to EO13
AND NNDSD ROMC
}
FDN.24 {@According to EO14_1
XOR NNDS02T NNDS38T
}
FDN.25 {@According to EO14_2
AND VTN0 NNDD
}
//|------------|
//|FDC CHECKS|
//|------------|
GROUP GFDC FDC?
NCDD = ND INSIDE NCDNW
NCDS = ND CUT NCDNW
NCDG = NCDS AND ALLPOLY
NCDPOLY = ALLPOLY ENCLOSE NCDG
NCDS_POLY = NCDPOLY AND NCDS
NCDL = NCDS_POLY NOT NCDNW
NCDDCON = NCDD AND COT
NCDSCON = NCDS AND COT
NCDSD = NCDD OR NCDS
NCDSD_OS = SIZE NCDSD BY 0.3
NCDSDD = SIZE NCDSD_OS BY -0.3
NCDS_EX_DG = NCDS NOT NCDG
NCDS1 = NCDS_EX_DG TOUCH NCDG == 1
NCDS2 = NCDS_EX_DG TOUCH NCDG == 2
NCDSC1 = NCDS1 AND NCDSCON
NCDSC2 = NCDS2 AND NCDSCON
NCDSD_OS399 = SIZE NCDSD BY 3.99
NCDSD_OSPD = NCDSD_OS399 AND PD
NCDDM = NCDSD_OS399 NOT PD
NCDPF = PD ENCLOSE NCDSD_OSPD
NCDD15 = SIZE NCDD BY 0.36
NCDD15T = NCDD15 TOUCH NCDPOLY
FDC.1 {@According to EC01_1;NS AND NW
A = NCDS AND NCDNW
INT A < 0.6 ABUT<90 SINGULAR REGION
}
FDC.2 {@According to EC01_2;NS AND NW
A = NCDS AND NCDNW
B = SIZE A BY -0.3
SIZE B BY 0.3
}
FDC.3 {@According to EC02_1 OLY OVER NS
ENC NCDS NCDPOLY < 0.24 ABUT<90 SINGULAR REGION
}
FDC.4 {@According to EC02_2OLY OVER NS
TMP1 = SIZE NCDS BY 0.24
TMP2 = NCDPOLY NOT TMP1
TMP3 = NCDPOLY AND TMP1
TMP4 = TMP3 TOUCH TMP2 == 2
TMP3 NOT TMP4
}
FDC.5 {@According to EC03_1
ENC NCDDCON NCDD < 1.02 ABUT<90 SINGULAR REGION
}
FDC.6 {@According to EC03_2
TMP1 = SIZE NCDD BY -1.022
TMP2 = NCDDCON NOT TMP1
TMP3 = NCDDCON AND TMP1
TMP4 = TMP3 TOUCH TMP2 == 2
TMP3 NOT TMP4
}
FDC.7 {@According to EC04_1
EXT NCDSCON NCDPOLY < 0.57 ABUT<90 SINGULAR REGION
}
FDC.8 {@According to EC04_2;GATE-CT
A = SIZE NCDG BY 0.57
B = NCDSC1 TOUCH A == 1
NOT NCDSC1 B
}
FDC.9 {@According to EC04_3;GATE-CT
A = SIZE NCDG BY 0.57
B = NCDSC2 TOUCH A == 2
NOT NCDSC2 B
}
FDC.10 {@According to EC05
ENC NCDSCON NCDS < 0.78 ABUT<90 SINGULAR REGION
}
FDC.11 {@According to EC06;GR WIDTH
A = PD ENCLOSE NCDSD_OSPD
INT A < 2.16 ABUT<90 SINGULAR REGION
}
FDC.12 {@According to EC07_1;NS-GR
EXT NCDS PD < 3.96 ABUT<90 SINGULAR REGION
}
FDC.13 {@According to EC07_2;ND-GR
EXT NCDD PD < 3.96 ABUT<90 SINGULAR REGION
}
FDC.14 {@According to EC07_3
A = HOLES NCDSD_OSPD
B = A NOT NCDSD_OSPD
C = B INSIDE NCDDM
D = NCDDM INSIDE C
NCDDM NOT D
}
FDC.15 {@According to EC08_1;NW-GR
EXT NCDNW PD < 2.94 ABUT<90 SINGULAR REGION
}
FDC.16 {@According to EC08_2
NCDPF_OS = SIZE NCDPF BY 2.97
A = NCDNW AND NCDPF_OS
B = NCDNW NOT NCDPF_OS
C = B TOUCH A == 2
NOT B C
}
FDC.17 {@According to EC09;ENDCAP
ENC NCDSDD NCDPOLY < 0.36 ABUT<90 SINGULAR REGION
}
FDC.18 {@According to EC10_1;NW OVER FD
ENC NCDSDD NCDNW < 1.02 ABUT<90 SINGULAR REGION
}
FDC.19 {@According to EC10_2
A = SIZE NCDSDD BY 1.02
NOT NCDNW A
}
FDC.20 {@According to EC11 ; IOPW+IONW ONLI
A = IOPW ENCLOSE NCDNW
B = IONW ENCLOSE NCDNW
XOR A B
}
FDC.21 {@According to EC12_1;FD-PO
EXT NCDD NCDPOLY < 0.36 ABUT<90 SINGULAR REGION
}
FDC.22 {@According to EC12_2
NOT NCDD15 NCDD15T
}
FDC.23 {@According to EC13;DIFF+CODE ONLI
A = IOWEL AND ROMC
FDCD = ROMC ENCLOSE A
T1 = FDCD ENCLOSE NCDSDD
T2 = NCDSDD ENCLOSE FDCD
XOR T1 T2
}
FDC.24 {@According to EC14;38ERR CHK
AND NCDSD VTN0
}
//|------------|
//|EVPP CHECKS|
//|------------|
GROUP GEVPR EVPR?
EVP_IOW = IOPW NOT IONW
EVP_IOP = IOPW ENCLOSE EVP_IOW
EVP_RNW_1 = IONW INSIDE EVP_IOP
EVP_RND = ND INSIDE EVP_RNW_1
EVP_RNW = EVP_RNW_1 ENCLOSE EVP_RND
EVP_RPW = IOPW ENCLOSE EVP_RND
EVP_RCOT = COT AND EVP_RND
EVP_RME1 = ME1 AND EVP_RND
EVP_RNDEDGE = NOT ANGLE EVP_RND >43<48
EVPR.1 {@N WELL OVER N+ DIFF IS 2.4
A1 = SIZE EVP_RNW BY -2.39
A2 = SIZE EVP_RNW BY -2.41
NOT INSIDE EVP_RND A1
NOT INSIDE A2 EVP_RND
}
EVPR.2 {@N WELL EDGE TO P WELL EDGE SPACING IS 2.4
A1 = SIZE EVP_RPW BY -2.39
A2 = SIZE EVP_RPW BY -2.41
NOT INSIDE EVP_RNW A1
NOT INSIDE A2 EVP_RNW
}
EVPR.3 {@N+ DIFF OVERLAP CONTACT Min is 1.86
ENC EVP_RCOT EVP_RNDEDGE < 1.86 ABUT<90 REGION
}
//EVPR.4 {@Contact Size ,
// @Already existed in SCOT RULE
//}
EVPR.5 {@N+ DIFF CORNER RULE 1.2
@1.2 * 1.414 = 1.696
A = ANGLE EVP_RND >44<46
NOT LENGTH A >1.69<1.70
}
EVPR.6 {@RESISTANCE LENGTH IS 6.66
A = EXT EVP_RCOT < 6.66 ABUT<90 SINGULAR REGION
A CUT EVP_RME1
B = SIZE EVP_RCOT BY 3.33
INTERACT EVP_RND B > 1
}
EVPR.7 {@RESISTENCE WIDTH IS 57.6
@ 1.2 + x = 1.2/1.414 + x * 1.414
@0.6*(2-1.414)/(1.414-1)=0.85
@1.2 + 0.85 = 2.05
A = SIZE EVP_RND BY -2.05
B = LENGTH A == 53.5
C = EXPAND EDGE B INSIDE BY 2
EVP_RND NOT INTERACT C
}
GROUP GEVPD EVPD?
IOPW_EX_EVPR = IOPW NOT EVP_IOP
IOWAND = IOPW_EX_EVPR AND IONW
IOWND = IOWAND ENCLOSE ND
EVP_DPW = IOWND NOT INTERACT ALLPOLY
EVP_DND = ND INSIDE EVP_DPW
EVP_DNW = IONW ENCLOSE EVP_DND
EVPD.1 {@N DIFF WIDTH is 2.52
INT EVP_DND < 2.52 ABUT<90 SINGULAR REGION
A = SIZE EVP_DND BY -1.26
SIZE A BY 1.26
}
EVPD.2 {@NWELL OVERLAP N+ DIFF is 0.54
ENC EVP_DND EVP_DNW < 0.54 ABUT<90 SINGULAR REGION
A = EVP_DNW NOT EVP_DND
B = SIZE A BY -0.27
C = SIZE B BY 0.27
C AND A
}
EVPD.3 {@NWELL CORNER RULE
A = ANGLE EVP_DNW >44<46
NOT LENGTH A >0.76<0.77
}
EVPD.4 {@PWELL OVERLAP P DIFF IS 2.28
EXT EVP_DNW PD < 2.28 ABUT<90 SINGULAR REGION
A = SIZE EVP_DNW BY 2.28
NOT TOUCH A PD
}
EVPD.5 {@P+ DIFF WIDTH is 2.16
A = SIZE EVP_DNW BY 2.28
B = TOUCH PD A
INT B < 2.16 ABUT<90 SINGULAR REGION
}
//EVPD.6 {@Contact Size ,
// @Already existed in SCOT RULE
//}
EVPD.7 {@Diode width is 3.6
INT EVP_DNW < 3.6 ABUT<90 PARALLEL ONLY SINGULAR REGION
INT EVP_DPW < 3.6 ABUT<90 PARALLEL ONLY SINGULAR REGION
}
EVPD.8 {@AREA of Diode must be more than 1332.072um2
A = SIZE EVP_DPW BY -1
B = SIZE A BY 1
AREA B < 1332.07
}
#ENDIF
这是DRC文件 完整的 |
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发表于 2012-4-26 21:11:35
