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高薪 诚聘
FPGA Verification Engineer要求: Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
Familiar with Verilog and SystemVerilog, VHDL isa plus. SystemVerilog and OVM(VMMor UVM) are needed skills for our verification engineers
工作地点:北京/上海
有意者可将简历投往该邮箱:Merry.Long@cn.flextronics.com
联系方式:18221687238
长期有效
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