On-Chip ESD Detection Circuit for System-Level ESDProtection Design

semico_ljj

invited paper

On-Chip ESD Detection Circuit for System-Level ESDProtection Design

Ming-Dou Ker 1, 2, Wan-Yen Lin1, Cheng-Cheng Yen1, Che-Ming Yang3, Tung-Yang Chen3,
and Shih-Fan Chen3

1 Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
2 Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan
3 Research and Development Center, Himax Technologies, Inc., Tainan, Taiwan

Abstract
A new on-chip CR-based electrostatic discharge (ESD)
detection circuit for system-level ESD protection design
is proposed in this work. The circuit performance to
detect positive or negative electrical transients generated
by system-level ESD tests has been analyzed in HSPICE
simulation and verified in silicon chip. The experimental
results in a 0.13-m CMOS process have confirmed that
the proposed detection circuit can detect ESD-induced
transient disturbance during system-level ESD zapping.
The detection results can be used as system recovery
firmware index to improve the immunity of CMOS IC
products against system-level ESD stress.

allen_tang

顶LZ，system ESD确实难。

liuzhieetop

多谢楼主分享！

inter211

下载看看，谢谢楼主

oscargo

感謝樓主

happywith123us

不错的东西

ni2121

为啥不搞个百度盘？那样下着还方便

ni2121

thanks

pennyxm

thank you very much

binnq

感谢