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楼主 |
发表于 2012-2-23 13:32:41
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谢谢jackertja 的回复，不过问题的关键是编译通过了，综合也没问题。ISE12.3
一下是这个文件,
-------------------------------------------------------------------------------
-- DESIGN NOTES:
-- Structural file.
--
-------------------------------------------------------------------------------
-- Revision history:
-- June 2010 Pascal Boudreau
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.math_ext_pkg.all;
use work.conv_ext_pkg.all;
use work.cpuconst_pkg.all;
use work.fpga_system_pkg.all;
use work.mcu_if_pkg.all;
use work.adc_acq_pkg.all;
use work.awg_cal_tbl_pkg.all;
use work.awg_if_pkg.all;
use work.pd_if_pkg.all;
use work.reg_DR_based_pkg.all;
use work.pd_hex_to_dbm_conv_pkg.all;
use work.reg_BRAM16K_based_pkg.all;
use work.cl_lp_ctl_pkg.all;
use work.voa_pwm_pkg.all;
use work.alarm_monitor_pkg.all;
use work.reg_pkg.all;
library unisim;
use unisim.vcomponents.all;
architecture rtl of AAAAA is
-----------------------------------------------------------------------------
-- Constant
-----------------------------------------------------------------------------
constant NB_INPUTS : integer := 15;
constant NB_OUTPUTS : integer := 123;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
type status_typ is array (0 to NB_AWG-1) of std_logic_vector(8 downto 0);
-----------------------------------------------------------------------------
-- FPGA System outputs
-----------------------------------------------------------------------------
signal RST : std_logic; -- internally generated reset
signal CLK_50MHZ : std_logic;
-----------------------------------------------------------------------------
-- MCU
-----------------------------------------------------------------------------
signal ADDR : std_logic_vector(15 downto 0); -- latched MCU address
signal D_MCU : std_logic_vector(15 downto 0);
signal WR : std_logic;
signal AD_o : std_logic_vector( 7 downto 0);
signal AD_i : std_logic_vector( 7 downto 0);
signal AD_t : std_logic_vector( 7 downto 0);
signal NOE : std_logic;
-----------------------------------------------------------------------------
-- ADC Acquisition outputs
-----------------------------------------------------------------------------
signal current_slot : std_logic_vector(5 downto 0);
signal next_slot : std_logic_vector(5 downto 0);
signal dack : std_logic_vector(0 downto 0);
signal drdy : std_logic_vector(0 downto 0);
signal data : adc_pdata;
signal cal_data : std_logic_vector(15 downto 0);
signal cal_data_i : std_logic_vector(15 downto 0);
signal ADC_DAT_i : std_logic;
signal ADC_CS_N_o : std_logic;
signal ADC_CLK_o : std_logic;
signal dack_concat : std_logic_vector(NB_AWG downto 0);
-----------------------------------------------------------------------------
-- AWG
-----------------------------------------------------------------------------
-- Glue
signal awg_reg_en : std_logic_vector(NB_AWG-1 downto 0);
signal pwm_load : std_logic_vector(NB_AWG-1 downto 0);
signal pwm_period_cnt : std_logic_vector(AWG_PWM_WIDTH_CONST-1 downto 0);
-- Output
signal STATUS : status_typ;
signal TEMP : temp_typ;
signal AWG_o : std_logic_vector(NB_AWG-1 downto 0);
-- Input
signal dack_awg : std_logic_vector(NB_AWG-1 downto 0);
signal drdy_awg : std_logic_vector(NB_AWG-1 downto 0);
signal drdy_awg_sr : std_logic_vector((3*NB_AWG)-1 downto 0);
-----------------------------------------------------------------------------
-- MUXPD
-----------------------------------------------------------------------------
signal muxpd_reg_en : std_logic;
signal MUX_PD_HEX : std_logic_vector(15 downto 0);
signal MUX_PD_CH_HEX : std_logic_vector(5 downto 0);
signal MUX_PD_STRB_HEX : std_logic;
signal dack_pd : std_logic;
signal drdy_pd : std_logic;
signal mux_sel_i : std_logic_vector(21 downto 0);
signal MUX_SEL_o : std_logic_vector(21 downto 0);
signal next_slot_conv : std_logic_vector(6 downto 0);
signal ts_mux_map_reg_en : std_logic;
signal ts_mux_map_reg0_en: std_logic;
signal ts_mux_map_reg1_en: std_logic;
-----------------------------------------------------------------------------
-- MUXPD conv
-----------------------------------------------------------------------------
signal muxpd_conv_reg_en : std_logic;
signal MUX_PD_DBM_VAL : std_logic_vector(15 downto 0);
signal MUX_PD_DBM_CH : std_logic_vector( 5 downto 0);
signal MUX_PD_DBM_STRB : std_logic;
signal pd_pwr_reg_en : std_logic;
signal muxpd_addr : std_logic_vector(10 downto 0);
signal pd_hex_val_conv : std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------
-- SVT
-----------------------------------------------------------------------------
signal cl_lp_strb : std_logic;
signal cl_lp_reg_en : std_logic;
signal avs_pwm_en : std_logic;
signal CL_LP_PASS_ADD : std_logic_vector( 1 downto 0);
signal CL_LP_PWM : std_logic_vector(15 downto 0);
signal CL_LP_PWM_CH : std_logic_vector( 6 downto 0);
signal CL_LP_PWM_STRB : std_logic;
signal cl_lp_pwm_strb_i : std_logic;
signal disable_sr : std_logic_vector( 1 downto 0);
-----------------------------------------------------------------------------
-- VOA PWM
-----------------------------------------------------------------------------
signal PWM_OUT : std_logic_vector(0 to NUMBER_OF_OUTPUTS_CONST-1);
signal voa_pwm_reg_en : std_logic;
-----------------------------------------------------------------------------
-- Alarm
-----------------------------------------------------------------------------
signal alarm_reg_en : std_logic;
signal alarm_strb : std_logic;
signal alarm_ch : std_logic_vector(5 downto 0);
signal ALARM_INT : std_logic;
-----------------------------------------------------------------------------
-- Registers and interrupts
-----------------------------------------------------------------------------
signal D_FPGA : std_logic_vector(15 downto 0);
signal top_reg_en : std_logic;
signal REV_SEL : std_logic;
signal IRQ_SEL : std_logic;
signal STATUS_SEL : std_logic;
signal IRM_SEL : std_logic;
signal CTL_SEL : std_logic;
signal SCRATCH_SEL : std_logic;
signal IRQ : std_logic_vector(15 downto 0);
signal IRM : std_logic_vector(15 downto 0);
signal GPIO : std_logic_vector(15 downto 0);
signal HTR_EN : std_logic;
-- IOBs
signal concat_inputs : std_logic_vector(NB_INPUTS-1 downto 0);
signal concat_inputs_buf : std_logic_vector(NB_INPUTS-1 downto 0);
signal concat_outputs : std_logic_vector(NB_OUTPUTS-1 downto 0);
signal concat_outputs_buf: std_logic_vector(NB_OUTPUTS-1 downto 0);
-- IN
signal RST_N_i : std_logic;
signal MCU_A_i : std_logic_vector(15 downto 8);
signal MCU_ALE1_i : std_logic;
signal MCU_WE_N_i : std_logic;
signal MCU_RE_N_i : std_logic;
signal MCU_FPGA_CE_N_i : std_logic;
signal DISABLE_i : std_logic;
-- OUT
signal MCU_INT_o : std_logic;
signal H_o : std_logic_vector(95 downto 0);
begin
-----------------------------------------------------------------------------
-- INPUTS
-----------------------------------------------------------------------------
concat_inputs <= (
DISABLE &
RST_N &
MCU_A &
MCU_ALE1 &
MCU_WE_N &
MCU_RE_N &
MCU_FPGA_CE_N &
ADC_DAT
);
IBUF_GEN: for i in 0 to NB_INPUTS-1 generate
IBUF_INST: IBUF
port map (
I => concat_inputs(i),
O => concat_inputs_buf(i)
);
end generate;
DISABLE_i <= concat_inputs_buf(14);
RST_N_i <= concat_inputs_buf(13);
MCU_A_i <= concat_inputs_buf(12 downto 5);
MCU_ALE1_i <= concat_inputs_buf(4);
MCU_WE_N_i <= concat_inputs_buf(3);
MCU_RE_N_i <= concat_inputs_buf(2);
MCU_FPGA_CE_N_i <= concat_inputs_buf(1);
ADC_DAT_i <= concat_inputs_buf(0);
-----------------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------------
concat_outputs <= MUX_SEL_o & MCU_INT_o & ADC_CS_N_o & ADC_CLK_o & AWG_o & H_o;
OBUF_GEN: for i in 0 to NB_OUTPUTS-1 generate
OBUF_INST: OBUF
generic map (
DRIVE => 2,
SLEW => "SLOW"
)
port map (
I => concat_outputs(i),
O => concat_outputs_buf(i)
);
end generate;
MUX_SEL <= concat_outputs_buf(122 downto 101);
MCU_INT <= concat_outputs_buf(100);
ADC_CS_N <= concat_outputs_buf(99);
ADC_CLK <= concat_outputs_buf(98);
AWG <= concat_outputs_buf(97 downto 96);
H <= concat_outputs_buf(95 downto 0);
-----------------------------------------------------------------------------
-- INOUTS
-----------------------------------------------------------------------------
AD_BUF_GEN: for i in 0 to 7 generate
AD_INST: IOBUF
generic map (
DRIVE => 4,
SLEW => "SLOW"
)
port map (
IO => MCU_AD(i),
I => AD_o(i),
O => AD_i(i),
T => AD_t(i)
);
end generate;
-----------------------------------------------------------------------------
-- Clock management, reset & startup
-----------------------------------------------------------------------------
FPGA_SYSTEM_INSTANCE: FPGA_SYSTEM
port map (
RSTIN => RST_N_i, -- IN
CLKIN => CLK_25M, -- IN
RST => RST, -- OUT
CLK => open, -- OUT
CLK_HALF => open, -- OUT
CLK_DOUBLE => CLK_50MHZ -- OUT
);
-----------------------------------------------------------------------------
-- MCU interface
-----------------------------------------------------------------------------
MCU_IF_INSTANCE: MCU_IF
port map (
RST => RST, -- IN
CLK50 => CLK_50MHZ, -- IN
-- IO Interface
MSn => '1', -- IN
CSn => MCU_FPGA_CE_N_i,-- IN
WEn => MCU_WE_N_i, -- IN
REn => MCU_RE_N_i, -- IN
ALE1 => MCU_ALE1_i, -- IN
A => MCU_A_i, -- IN
AD_I => AD_i, -- IN
AD_O => AD_o, -- OUT
AD_T => AD_t, -- OUT
-- Core interface
D_FPGA => D_FPGA, -- IN
ADDR => ADDR, -- OUT
D_MCU => D_MCU, -- OUT
WR => WR -- OUT
);
NOE <= MCU_RE_N_i;
-----------------------------------------------------------------------------
-- ADC Acquisition
-----------------------------------------------------------------------------
dack_concat <= dack_awg & dack_pd;
dack(0) <= or_reduce(dack_concat);
adc_acq_1: adc_acq
generic map (
MAX_SLOT => 64,
SLOT_WIDTH => 6,
CLK_DIVIDER => 3125
)
port map (
RST => RST,
CLK => CLK_50MHZ,
-- Core interface
SLOT => "0111111110111111011111110011111101111111001111110111111110111111",
DACK => dack,
CURRENT_SLOT => current_slot,
NEXT_SLOT => next_slot,
DRDY => drdy,
DATA => data,
INTERVAL => open,
-- ADC Interfrace
ADC_DATA(0) => ADC_DAT_i,
ADC_CSn => ADC_CS_N_o,
ADC_CLK => ADC_CLK_o
);
-----------------------------------------------------------------------------
-- AWG temperature controllers
-----------------------------------------------------------------------------
-- PWM start timer counter
PWM_PERIOD_CNT_PROC: process (RST, CLK_50MHZ)
begin
if RST = '1' then
pwm_period_cnt <= (others => '0');
drdy_awg_sr <= (others => '0');
elsif CLK_50MHZ'event and CLK_50MHZ = '1' then
pwm_period_cnt <= pwm_period_cnt + 1;
drdy_awg_sr <= drdy_awg_sr((2*NB_AWG)-1 downto 0) & drdy_awg;
end if;
end process;
-- When more than one AWG, staggered the load
pwm_load(0) <= '1' when pwm_period_cnt = X"FF" else '0';
pwm_load(1) <= '1' when pwm_period_cnt = X"7F" else '0';
-- Register access
awg_reg_en(0) <= '1' when ADDR(15 downto 5) = AWG_A_BASE_CONST else '0';
awg_reg_en(1) <= '1' when ADDR(15 downto 5) = AWG_B_BASE_CONST else '0';
drdy_awg(0) <= '1' when conv_integer(current_slot) = 7 and drdy(0) = '1' else '0';
drdy_awg(1) <= '1' when conv_integer(current_slot) = 55 and drdy(0) = '1' else '0';
AWG_CAL_TABLE_INSTANCE: AWG_CAL_TABLE
generic map (
NB_DEC_BITS => 6
)
port map (
DO => cal_data_i,-- OUT
ADDR => data(0), -- IN
CLK => CLK_50MHZ, -- IN
RST => RST -- IN
);
-- Int portion from 15 downto 6.
-- Decimal portion from 5 downto 0.
-- We need only 5 downto 2, so we extend the integer portion to 12 bits.
cal_data <= cal_data_i(15) & cal_data_i(15) & cal_data_i(15 downto 2);
AWG_GEN: for i in 0 to NB_AWG-1 generate
AWG_IF_INSTANCE: awg_if
generic map (
AWG_PWM_WIDTH => AWG_PWM_WIDTH_CONST
)
port map (
RST => RST, -- IN System reset (async)
CLK => CLK_50MHZ, -- IN 50 MHz clock
-- Config and status
UND => '0', -- IN Low current sensor
OVR => '0', -- IN High current sensor
OT_CA_EN => GPIO(2), -- IN Enable the CA when OT is detected
AWG_EN => GPIO(4+i), -- IN
PWM_LOAD => pwm_load(i),-- IN
AWG => AWG_o(i), -- OUT
STATUS => STATUS(i), -- OUT
TEMP => TEMP(i), -- OUT
-- CPU Interface
MCU_EN => awg_reg_en(i), -- IN
ADDR => ADDR(4 downto 1), -- IN
D_MCU => D_MCU, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_FPGA => D_FPGA, -- OUT
--
DRDY => drdy_awg_sr(i + (2*NB_AWG)),
CAL_DATA => cal_data,
DACK => dack_awg(i)
);
end generate;
-----------------------------------------------------------------------------
-- Multiplexed PD monitors
-----------------------------------------------------------------------------
muxpd_reg_en <= '1' when ADDR(15 downto 8) = PD_BASE_CONST else '0';
drdy_pd <= drdy(0) when
-- PD
conv_integer(current_slot(2 downto 0)) < 6 or
-- SPD
conv_integer(current_slot) = 14 or
conv_integer(current_slot) = 30 or
conv_integer(current_slot) = 46 or
conv_integer(current_slot) = 62
else '0';
PD_IF_INSTANCE: PD_IF
generic map (
LAST_TIME_SLOT => 62,
TIMESLOT_WIDTH => 6
)
port map (
RST => RST,
CLK => CLK_50MHZ,
AVG_EN => GPIO(10),
AVG_NO => GPIO(9 downto 8),
-- ADC Interface
ADC_DATA => data(0),
DRDY => drdy_pd,
TIMESLOT => current_slot,
DACK => dack_pd,
-- To HEX2DBM Converter
PD_HEX => MUX_PD_HEX,
PD_CH => MUX_PD_CH_HEX,
PD_STRB => MUX_PD_STRB_HEX,
-- MCU Interface
MCU_EN => muxpd_reg_en,
ADDR => ADDR(7 downto 1),
D_MCU => D_MCU,
WR => WR,
NOE => NOE,
D_FPGA => D_FPGA
);
ts_mux_map_reg_en <= '1' when ADDR(15 downto 8) = MUX_MAP_BASE_CONST else '0';
next_slot_conv <= next_slot & '0';
ts_mux_map_reg0_en <= ts_mux_map_reg_en and not ADDR(7);
reg_DR_based_1: reg_DR_based
generic map (
ADDR_WIDTH => 7,
NB_RAM => 4,
DATA_WIDTH => 16
)
port map (
CLK => CLK_50MHZ,
RST => RST,
-- Cpu port
EN_MCU => ts_mux_map_reg0_en,
ADDR => ADDR(6 downto 1),
D_MCU => D_MCU,
WR => WR,
NOE => NOE,
D_FPGA => D_FPGA,
-- Core port
ADDR_B => next_slot_conv,
RDATA_B => mux_sel_i(15 downto 0)
);
ts_mux_map_reg1_en <= ts_mux_map_reg_en and ADDR(7);
reg_DR_based_2: reg_DR_based
generic map (
ADDR_WIDTH => 7,
NB_RAM => 4,
DATA_WIDTH => 6
)
port map (
CLK => CLK_50MHZ,
RST => RST,
-- Cpu port
EN_MCU => ts_mux_map_reg1_en,
ADDR => ADDR(6 downto 1),
D_MCU => D_MCU,
WR => WR,
NOE => NOE,
D_FPGA => D_FPGA,
-- Core port
ADDR_B => next_slot_conv,
RDATA_B => mux_sel_i(21 downto 16)
);
MUX_SEL_PROC: process (RST, CLK_50MHZ)
begin
if RST = '1' then
MUX_SEL_o <= (others => '0');
elsif CLK_50MHZ'event and CLK_50MHZ = '1' then
MUX_SEL_o <= mux_sel_i;
end if;
end process;
-----------------------------------------------------------------------------
-- MUXPD CONV HEX TO DBM and store
-----------------------------------------------------------------------------
muxpd_conv_reg_en <= '1' when ADDR(15 downto 12) = CONV_BASE_CONST else '0';
pd_hex_val_conv <= "00" & MUX_PD_HEX(15 downto 2);
PD_HEX_TO_DBM_CONV_INSTANCE: pd_hex_to_dbm_conv
port map (
RST => RST, -- IN
CLK => CLK_50MHZ, -- IN
--
MCU_EN => muxpd_conv_reg_en,-- IN
ADDR => ADDR(11 downto 1),-- IN
D_MCU => D_MCU, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_FPGA => D_FPGA, -- OUT
--
PD_RAW_VAL => pd_hex_val_conv, -- IN
PD_RAW_CH => MUX_PD_CH_HEX, -- IN
PD_RAW_STRB => MUX_PD_STRB_HEX, -- IN
PD_DBM_VAL => MUX_PD_DBM_VAL, -- OUT
PD_DBM_CH => MUX_PD_DBM_CH, -- OUT
PD_DBM_STRB => MUX_PD_DBM_STRB -- OUT
);
pd_pwr_reg_en <= '1' when ADDR(15 downto 8) = PWR_BASE_CONST else '0';
muxpd_addr <= "0000" & MUX_PD_DBM_CH & '0';
PD_PWR_DB_TBL_INSTANCE: reg_BRAM16K_based
port map (
CLK => CLK_50MHZ, -- IN
RST => RST, -- IN
-- CPU Port
EN_MCU => pd_pwr_reg_en, -- IN
ADDR => ADDR(10 downto 1), -- IN
D_MCU => D_MCU, -- IN
WR => '0', -- IN
NOE => NOE, -- IN
D_FPGA => D_FPGA, -- OUT
-- PortA -> Write Core Port.
-- It is shared with the CPU write port.
RE_A => '0',
DATA_A => x"0000",
WE_A => '0',
ADDR_A => "00000000000",
RDATA_A => open,
-- Core access
RE_B => '1',
DATA_B => MUX_PD_DBM_VAL, -- IN
ADDR_B => muxpd_addr, -- IN
WE_B => MUX_PD_DBM_STRB, -- IN
RDATA_B => open -- OUT
);
-----------------------------------------------------------------------------
-- SVT
-----------------------------------------------------------------------------
DEBOUCE_PROC: process (RST, CLK_50MHZ)
begin
if RST = '1' then
disable_sr <= (others => '0');
elsif CLK_50MHZ'event and CLK_50MHZ = '1' then
disable_sr <= disable_sr(0) & DISABLE_i;
end if;
end process;
cl_lp_reg_en <= '1' when ADDR(15 downto 14) = CLO_BASE_CONST else '0';
-- We put in AVS when disable or under temp and CA enabled.
avs_pwm_en <= disable_sr(1) or ((STATUS(0)(8) or STATUS(1)(8)) and GPIO(1));
cl_lp_strb <= MUX_PD_DBM_STRB when MUX_PD_DBM_CH < "110000" else '0';
CL_LP_CTL_INSTANCE : CL_LP_CTL
port map (
RST => RST,
CLK => CLK_50MHZ,
MCU_EN => cl_lp_reg_en, -- IN
ADDR => ADDR(13 downto 1), -- IN
D_MCU => D_MCU, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_FPGA => D_FPGA, -- OUT
LR_MODE => '1',
MUX_PD_DBM => MUX_PD_DBM_VAL, -- IN MUX PD dbm value for current channel
MUX_PD_CH_DBM => MUX_PD_DBM_CH, -- IN MUX PD channel number for MUX_PD_DBM
MUX_PD_STRB_DBM => cl_lp_strb, -- IN MUX PD strobe pulse for MUX_PD_DBM
-- value (no more than one clock cycle every 256 clocks)
DISABLE => avs_pwm_en,
DELTA_SIGN => GPIO(12),
PROT_REC_CH_EN => GPIO(11),
CL_LP_PASS_ADD => CL_LP_PASS_ADD, -- OUT 0 when current channel PASS mode 1 when ADD mode
CL_LP_PWM => CL_LP_PWM, -- OUT PWM set point for current channel
CL_LP_PWM_CH => CL_LP_PWM_CH, -- OUT SVT PWM Channel number
CL_LP_PWM_STRB => CL_LP_PWM_STRB -- OUT 1 when SVT PWM strobe (one clock cycle)
-- This signal can't be active more than once every 256 clock cycles
);
-----------------------------------------------------------------------------
-- Heaters
-----------------------------------------------------------------------------
-- If using more than 1 module, the address filtering is done at this level.
voa_pwm_reg_en <= '1' when ADDR(13 downto 11) = PWM_BASE_CONT and cl_lp_reg_en = '1' else '0';
cl_lp_pwm_strb_i <= CL_LP_PWM_STRB and not GPIO(3);
-- We disable the PWM if under temp + CA_EN or when the global is 0
HTR_EN <= GPIO(0);
VOA_PWM_INSTANCE: VOA_PWM
generic map (
NUMBER_OF_CHANNELS => NUMBER_OF_CHANNELS_CONST,
NUMBER_OF_OUTPUTS => NUMBER_OF_OUTPUTS_CONST,
PWM_WIDTH => PWM_WIDTH_CONST,
DELAY_BETWEEN_OUTPUT => DELAY_BETWEEN_OUTPUT_CONST
)
port map (
RST => RST,
CLK_50MHZ => CLK_50MHZ,
-- CPU Interface
EN_MCU => voa_pwm_reg_en, -- IN
ADDR => ADDR(10 downto 1), -- IN
D_MCU => D_MCU, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_FPGA => D_FPGA, -- OUT
--
VOL_COMP => "000100000000000000",
PWM_VALID => cl_lp_pwm_strb_i,
PWM_VALUE => CL_LP_PWM,
PWM_CH => CL_LP_PWM_CH,
HTR_EN => HTR_EN,
PWM_OUT => PWM_OUT
);
-- Mapping of PWM to heaters done inside
H_o <= PWM_OUT;
-----------------------------------------------------------------------------
-- Alarm
-----------------------------------------------------------------------------
alarm_reg_en <= '1' when ADDR(15 downto 10) = ALM_BASE_CONST else '0';
alarm_strb <= dack_awg(0) or dack_awg(1) or MUX_PD_DBM_STRB;
alarm_ch <= MUX_PD_DBM_CH when dack_awg = "00" else MUX_PD_CH_HEX;
ALARM_MONITOR_INSTANCE : ALARM_MONITOR
generic map(
REFRESH_CNT => 1
)
port map (
RST => RST,
CLK => CLK_50MHZ,
ADDR => ADDR(9 downto 1), -- IN
D_MCU => D_MCU, -- IN
D_FPGA => D_FPGA, -- OUT
MCU_EN => alarm_reg_en,
WR => WR, -- IN
NOE => NOE, -- IN
TEMP => TEMP, -- IN temperature of AWG A (sampled when MUX_PD_CH_DBM = 49
ALARM_INT => ALARM_INT, -- OUT Interrupt generated by the Alarm module
MUX_PD_DBM => MUX_PD_DBM_VAL, -- IN MUX PD dbm value (ch 0-39) individual PD (ch 40-41)
MUX_PD_CH_DBM => alarm_ch, -- IN MUX PD channel number for MUX_PD_DBM
MUX_PD_STRB_DBM => alarm_strb -- IN MUX PD valid pulse for MUX_PD_DBM value
);
-----------------------------------------------------------------------------
-- Top-level Registers
-----------------------------------------------------------------------------
top_reg_en <= '1' when ADDR(15 downto 4) = TOP_BASE_CONST else '0';
REV_SEL <= '1' when ADDR(3 downto 1) = REV_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
IRQ_SEL <= '1' when ADDR(3 downto 1) = IRQ_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
IRM_SEL <= '1' when ADDR(3 downto 1) = IRM_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
CTL_SEL <= '1' when ADDR(3 downto 1) = CTL_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
SCRATCH_SEL <= '1' when ADDR(3 downto 1) = SCRATCH_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
STATUS_SEL <= '1' when ADDR(3 downto 1) = STATUS_ADDR_BASE_CONST/2 and top_reg_en = '1' else '0';
IRQ(0) <= '1' when IRM(0) = '1' and STATUS(1)(7) = '1' else '0';
IRQ(1) <= '1' when IRM(1) = '1' and STATUS(0)(7) = '1' else '0';
IRQ(2) <= '1' when IRM(2) = '1' and STATUS(1)(8) = '1' else '0';
IRQ(3) <= '1' when IRM(3) = '1' and STATUS(0)(8) = '1' else '0';
IRQ(4) <= '1' when IRM(4) = '1' and ALARM_INT = '1' else '0';
IRQ(15 downto 5) <= (others => '0');
IRM_REG_INSTANCE: DBREG
generic map (
RST_VALUE => X"0000",
MASK => X"001F"
)
port map (
C => CLK_50MHZ, -- IN
RST => RST, -- IN
EN_MCU => IRM_SEL, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_MCU => D_MCU, -- IN
D_FPGA => D_FPGA, -- OUT
Q => IRM -- OUT
);
-- control register
CTL_REG_INSTANCE: dbreg
generic map (
RST_VALUE => X"0000",
MASK => X"1f3f"
)
port map (
C => CLK_50MHZ, -- IN
RST => RST, -- IN
EN_MCU => CTL_SEL, -- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_MCU => D_MCU, -- IN
D_FPGA => D_FPGA, -- OUT
Q => GPIO -- OUT
);
SCRATCH_REG_INSTANCE: dbreg
generic map (
RST_VALUE => X"0000" -- default value
)
port map (
C => CLK_50MHZ, -- IN
RST => RST, -- IN
EN_MCU => SCRATCH_SEL,-- IN
WR => WR, -- IN
NOE => NOE, -- IN
D_MCU => D_MCU, -- IN
D_FPGA => D_FPGA, -- OUT
Q => open
);
-----------------------------------------------------------------------------
-- Drive outputs
-----------------------------------------------------------------------------
D_FPGA <= REV_MAJOR_CONST & REV_MINOR_CONST when REV_SEL = '1' and NOE = '0' else
(others => 'Z');
D_FPGA <= IRQ when IRQ_SEL = '1' and NOE = '0' else (others => 'Z');
D_FPGA <= "000000000000000" & disable_sr(1) when STATUS_SEL = '1' and NOE = '0' else (others => 'Z');
INT_PIPELINE_PROC: process (CLK_50MHZ,RST)
begin
if RST = '1' then
MCU_INT_o <= '0';
elsif CLK_50MHZ'event and CLK_50MHZ = '1' then
if IRQ(4 downto 0) = "00000" then
MCU_INT_o <= '1';
else
MCU_INT_o <= '0';
end if;
end if;
end process;
end rtl;
D_FPGA 在很多地方被驱动了，文件没有问题，已经下载跑了，望高手解释一下。谢谢！虽然做了5年的FPGA，但VHDL从来没怎么关注。 |
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发表于 2012-2-23 10:30:05
发表于 2012-2-23 10:44:46
