assign f_wrclk = clk ;
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ncelab: *W,SDFNCAP (../rtl/EXJ007_hht.v,1144235|5): The interconnect source tb_top.visionchip.top_core.CTSCLKINVX32M_G2B1I65.Y is separated by a unidirectional continuous assign from the destination tb_top.visionchip.top_core.can0.outFIFO.rp_s_reg_4_.CK. The port annotation will still occur.