IEEE－Design for HighSpeed HighResolution Comparators（Razavi1992）

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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27,NO. 12,DECEMBER 1992

Design Techniques for High-Speed, High-Resolution Comparators

by
Behzad Razavi, Member, IEEE, and Bruce A. Wooley, Fellow, IEEE

Abstract
    This paper describes precision techniques for the
design of comparators used in high-performance analog-to-digital
converters employing parallel conversion stages. Following
a review of conventional offset cancellation techniques, circuit
designs achieving 12-b resolution in both BiCMOS and CMOS
5-V technologies are presented. The BiCMOS comparator consists
of a preamplifier followed by two regenerative stages and
achieves an offset of 200 pV at a 1O-MHZ clock rate while dissipating
1.7 mW. In the CMOS comparator offset cancellation
is used in both a single-stage preamplifier and a subsequent
latch to achieve an offset of less than 300 pV at comparison
rates as high as 10 MHz, with a power dissipation of 1.8 mW.

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