dft hold time violation problem

yinic1987 · 发表于 2012-2-7 11:25:10

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In the design, both of posedge and negedge of clock is used.

dc automatically insert test_si for negedge of clock, as shown below

but the log report hold time for test_si violate:

--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
test_si2 (in) 0.00 0.00 r
tposemem/test_si2 (tposemem_test_1) 0.00 0.00 r
tposemem/Bisted_DPR64x16/test_si1 (Bisted_DPR64x16_test_1)
0.00 0.00 r
tposemem/Bisted_DPR64x16/BistCtrl_i0/test_si1 (BistCtrl_DPR64x16_test_1)
0.00 0.00 r
tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/test_si (ST_MAG_DPR64x16_test_1)
0.00 0.00 r
tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/S5_reg[0]/SI (SDFFNHX8)
0.00 0.00 r
data arrival time 0.00
clock CLK (fall edge) 10.00 10.00
clock network delay (ideal) 0.00 10.00
tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/S5_reg[0]/CKN (SDFFNHX8)
0.00 10.00 f
library hold time 0.05 10.05
data required time 10.05
--------------------------------------------------------------------------
data required time 10.05
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -10.05

复制代码

the slack is about half of clock period.

How to solve the problem? Need i constraint test_si?

linuxluo · 发表于 2012-2-10 20:48:14

问题在于在实际设计中你的TEST-SI是有CLK还是CLKN驱动？
即便是CLK，你可以用LOCKUP LATCH解决

cmwtony · 发表于 2012-2-11 10:33:18

>>Need i constraint test_si?
YEs you should defined it is triggered CLK or CLKN

[求助] dft hold time violation problem

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