Cadence上海 招聘软件研发工程师/FPGA

kongxinluobo

以下四个职位对工作经验没有强制要求，原则上应届生要求博士或硕士，本科学历则至少需要两年以上工作经验。请将简历投递至 cecilyl@cadence.com

（一）Software Engineer for Hier Solution

Position Description:

1.
The candidate will be a member of the Encounter Hier Solution team in Shanghai, to work on the development and maintenance of Hier Solution project.

2.
The responsibilities include development of new features and products, and support other teams in Encounter product lines.

3.
The candidate must be comfortable working with existing code as well as developing new functionality to address new requirements, and be working closely with local/remote team members, and be also strong technical support to team.

Position Requirements:

1.
Candidate must be an expert in software engineering methods and committed to high quality of development work.

2.
The individual must be team-oriented, possess good communication skills, self-motivated, able to work independently and working with a team from multiple remote sites.

3.
Candidate must be able to develop detailed technical specification as well as the ability to scope efforts required.

4.
The candidate must be also smart to capture new EDA technologies, and switch among different areas successfully.

5.
Advanced developing and debugging software in
UNIX & LINUX environments, familiar with gnu c/c++, gdb etc..

6.
Strong problem-solving, architecture, algorithmic.

7.
Familiar with interpreted language such as TCL is a plus.

8.
Knowledge of Timing analysis is a plus.

（二）Software Engineer for Encounter Floorplan

Position Description:

1.
The candidate will be a member of the Encounter floorplan team in Shanghai, to work on the development and maintenance of manual Floorplan project.

2.
The responsibilities include the develop of new features and products, and support other teams in Encounter product lines.

3.
The candidate must be comfortable working with existing code as well as developing new functionality to address new requirements, and be working closely with local/remote team members, and be also strong technical support to team.

Position Requirements:

1.
Candidate must be an expert in software engineering methods and committed to high quality of development work.

2.
The individual must be team-oriented, possess good communication skills, self-motivated, able to work independently and working with a team from multiple remote sites.

3.
Candidate must be able to develop detailed technical specification as well as the ability to scope efforts required.

4.
The candidate must be also smart to capture new EDA technologies, and switch among different areas successfully.

5.
Advanced developing and debugging software in
UNIX & LINUX environments, familiar with gnu c/c++, gdb etc..

6.
Strong problem-solving, architecture, algorithmic.

7.
Familiar with interpreted language such as TCL is a plus.

8.
Knowledge of Digital Physical Design flow such as Floorplan/Placement/Routing/CTS is a plus.

（三）Software Engineer for Clock Tree Synthesis

Job Responsibility

1.
R&D engineer to do the clock tree synthesis related works (product maintain, software development, design flow improvement etc.)

Job Requirement

2.
MS or PhD in EE/CS etc.

3.
Excellent programming skills (C/C++, script)

4.
The following background is preferred: EDA, IC physical design, CTS, Timing analysis, Optimization.

5.
Good written and spoken English

6.
Good communication skills and be able to work within a team.

（四）Software Engineer for distributed computing:

Position Description:

1.
The candidate will be responsible for the development and maintenance of
distributed computing
infrastructure of Encounter platform in Cadence.

Position Requirements:

2.
MS or above in CS/EE with 3+ years of working experience or BS with 5+ years of working experience for Sr. Member of Technical Staff; MS or above in CS/EE or BS with 3+ years of working experience for Member of Technical Staff

3.
Programming skill on Linux/Unix platform is must.

4.
Strong C/C++ coding skill.

5.
Deep understanding on Linux/Unix OS

6.
Parallel computing programming skill is strongly expected.

7.
Tcl programming skill is a plus

8.
EDA software development experience is a plus.

9.
Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills

10.
Good English communication skill, both oral and written.

11.
Ph.D is a plus.

请注明你投递的职位，发送简历至cecilyl@cadence.com

(一)Senior Software Engineer for SPB team.

Position Description:

1.
The candidate will be a member of the SPB R&D team in HSTC, Shanghai, to work on the development and maintenance of high-speed projects.

2.
The responsibilities include the develop of new features and products, and support other team member in SPB high-speed product lines.

3.
The candidate must be comfortable working with existing code as well as developing new functionality to address new requirements, and be working closely with local/remote team members, and be also strong technical support to team.

Position Requirements:

1.
Candidate must be an expert in software engineering methods and committed to high quality of development work.

2.
The individual must be team-oriented, possess good communication skills, self-motivated, able to work independently and working with a team from multiple remote sites.

3.
Candidate must be able to develop detailed technical specification as well as the ability to scope efforts required.

4.
The candidate must be also smart to capture new EDA technologies, and switch among different areas successfully.

5.
Advanced developing and debugging software in Windows, UNIX & LINUX environments, including the C/C++ and VC .net programming and GUI design.

6.
Strong problem-solving, architecture, algorithmic, and GUI development abilities are a must.

7.
Familiar with interpreted language such as SKILL is a plus.

8.
Knowledge of SPB design tools such as: Layout Editor, Schematic Editor, Modeling and Measurement is a also plus.

（二）Senior FPGA Engineer

Position Description

1.
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.

  

Position Requirements

2.
The position requires BSEE, or equivalent, with a minimum of 4 yrs of industry experience in designing hardware systems.

3.
Must have excellent communication skills, both written and verbal.

4.
Technical expertise in FPGA design for either Altera or Xilinx products is required.

5.
Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.

6.
In addition RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.

7.
Verification using Cadence simulation products is desired.

8.
Experience with scripting languages like Perl, TCL C-shell is strongly recommended.

9.
Experience with PCB tools is also desired. Experience with high speed memory interface design is also desired.

（三）Hardware Engineer for Memory Modeling

Position Description:

1. Responsible for designing and developing models of system level memories like DDR SDRAM, NAND Flash, EEPROM and eMMC for use on hardware based verification products.

2. In addition modifying, updating, maintaining and productizing existing system level memory model products.

3. Perform as individual contributor involving RTL design, verification, productizing and documentation.

4. Work on moderately complex problems related to emulation, simulation or verification issues.

  

Position Requirements:

1. The position requires BSEE, or equivalent, with a minimum of 2 yrs of industry experience in designing hardware systems.

2. Must have excellent communication skills, both written and verbal.

3. RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.

4. In addition Verification using Cadence simulation products is desired as is Verification experience using emulation products.

5. Experience with scripting languages like Perl, TCL C-shell is strongly recommended.