用quartus 10.1 搭建一个DDR3的小工程,其sopc系统如下图所示,
SOPC系统生成后去做系统仿真是没问题的,但是在start Analysis & Synthesis 时,最后将要完成的时候,会出现如下错误,
Error: Termination logic block atom "uniphy_ddr3_0:the_uniphy_ddr3_0|uniphy_ddr3_0_controller_phy:controller_phy_inst|uniphy_ddr3_0_memphy_top:memphy_top_inst|uniphy_ddr3_0_oct_control:uoct_control|sd2a_0" uses SERIESTERMINATIONCONTROL port, which must be connected to SERIESTERMINATIONCONTROL port on an output buffer atom
Error: Termination logic block atom "uniphy_ddr3_0:the_uniphy_ddr3_0|uniphy_ddr3_0_controller_phy:controller_phy_inst|uniphy_ddr3_0_memphy_top:memphy_top_inst|uniphy_ddr3_0_oct_control:uoct_control|sd2a_0" uses PARALLELTERMINATIONCONTROL port, which must be connected to PARALLELTERMINATIONCONTROL port on an output buffer atom
还请搞过DDR的大哥大姐们,看看这个问题该什么解决........