|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
//------------------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- RobustVerilog version 1.5g (limited free version) Jul 5 2011
//-- Invoked Sun Oct 09 23:50:59 2011
//-- Source file: prgen_fifo.v
//-- Parent file: axi2ahb_cmd.v
//-- Project directory: D:/axi2ahb/robust_axi2ahb/trunk/run/
//-- Target directory: out/
//-- Command flags: ..\..\..\..\robust.exe ../robust_reg.pro -gui
//-- [url=http://www.provartec.com/edatools]www.provartec.com/edatools ... info@provartec.com
//------------------------------------------------------------------
module prgen_fifo(clk,reset,push,pop,din,dout,empty,full);
parameter WIDTH = 8;
parameter DEPTH_FULL = 8;
parameter SINGLE = DEPTH_FULL == 1;
parameter DEPTH = SINGLE ? 1 : DEPTH_FULL -1;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
parameter LAST_LINE = DEPTH-1;
input clk;
input reset;
input push;
input pop;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
output empty;
output full;
wire reg_push;
wire reg_pop;
wire fifo_push;
wire fifo_pop;
reg [DEPTH-1:0] full_mask_in;
reg [DEPTH-1:0] full_mask_out;
reg [DEPTH-1:0] full_mask;
reg [WIDTH-1:0] fifo [DEPTH-1:0];
wire fifo_empty;
wire next;
reg [WIDTH-1:0] dout;
reg dout_empty;
reg [DEPTH_BITS-1:0] ptr_in;
reg [DEPTH_BITS-1:0] ptr_out;
assign reg_push = push & fifo_empty & (dout_empty | pop);
assign reg_pop = pop & fifo_empty;
assign fifo_push = !SINGLE & push & (~reg_push);
assign fifo_pop = !SINGLE & pop & (~reg_pop);
always @(posedge clk or posedge reset)
if (reset)
begin
dout <= #1 {WIDTH{1'b0}};
dout_empty <= #1 1'b1;
end
else if (reg_push)
begin
dout <= #1 din;
dout_empty <= #1 1'b0;
end
else if (reg_pop)
begin
dout <= #1 {WIDTH{1'b0}};
dout_empty <= #1 1'b1;
end
else if (fifo_pop)
begin
dout <= #1 fifo[ptr_out];
dout_empty <= #1 1'b0;
end
always @(posedge clk or posedge reset)
if (reset)
ptr_in <= #1 {DEPTH_BITS{1'b0}};
else if (fifo_push)
ptr_in <= #1 ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
always @(posedge clk or posedge reset)
if (reset)
ptr_out <= #1 {DEPTH_BITS{1'b0}};
else if (fifo_pop)
ptr_out <= #1 ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
always @(posedge clk)
if (fifo_push)
fifo[ptr_in] <= #1 din;
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
full_mask_in = {DEPTH{1'b0}};
full_mask_in[ptr_in] = fifo_push;
end
always @(/*AUTOSENSE*/fifo_pop or ptr_out)
begin
full_mask_out = {DEPTH{1'b0}};
full_mask_out[ptr_out] = fifo_pop;
end
always @(posedge clk or posedge reset)
if (reset)
full_mask <= #1 {DEPTH{1'b0}};
else if (fifo_push | fifo_pop)
full_mask <= #1 (full_mask & (~full_mask_out)) | full_mask_in;
assign next = |full_mask;
assign fifo_empty = ~next;
assign empty = fifo_empty & dout_empty;
assign full = SINGLE ? !dout_empty : &full_mask;
endmodule
//------------------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- RobustVerilog version 1.5g (limited free version) Jul 5 2011
//-- Invoked Sun Oct 09 23:51:00 2011
//-- Source file: axi2ahb_wr_fifo.v
//-- Parent file: axi2ahb.v
//-- Project directory: D:/axi2ahb/robust_axi2ahb/trunk/run/
//-- Target directory: out/
//-- Command flags: ..\..\..\..\robust.exe ../robust_reg.pro -gui
//-- www.provartec.com/edatools ... info@provartec.com
//------------------------------------------------------------------
module axi2ahb_wr_fifo (clk,reset,WID,WDATA,WSTRB,WLAST,WVALID,WREADY,BID,BRESP,BVALID,BREADY,HWDATA,HREADY,HTRANS,HRESP,cmd_err,wdata_phase,wdata_ready,data_last);
parameter FIFO_LINES = 32; //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
input [3:0] WID;
input [31:0] WDATA;
input [32/8-1:0] WSTRB;
input WLAST;
input WVALID;
output WREADY;
output [3:0] BID;
output [1:0] BRESP;
output BVALID;
input BREADY;
output [32-1:0] HWDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input cmd_err;
input wdata_phase;
output wdata_ready;
input data_last;
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
wire resp_push;
wire resp_pop;
wire resp_empty;
wire resp_full;
reg [2:0] burst_cnt;
wire burst_full;
wire axi_last;
wire ahb_last;
wire [1:0] cmd_resp;
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
assign wdata_ready = burst_cnt > 'd0;
assign WREADY = (~data_full) & (~burst_full);
assign data_push = WVALID & WREADY;
assign data_pop = wdata_phase & HREADY;
assign axi_last = WVALID & WREADY & WLAST;
assign ahb_last = wdata_phase & data_last;
assign burst_full = burst_cnt == {3{1'b1}};
always @(posedge clk or posedge reset)
if (reset)
burst_cnt <= #1 'd0;
else if (axi_last | ahb_last)
burst_cnt <= #1 burst_cnt + axi_last - ahb_last;
prgen_fifo #(32, FIFO_LINES)
data_fifo(
.clk(clk),
.reset(reset),
.push(data_push),
.pop(data_pop),
.din({WDATA
}
),
.dout({HWDATA
}
),
.empty(data_empty),
.full(data_full)
);
assign resp_push = ahb_last;
assign resp_pop = BVALID & BREADY;
assign BVALID = (~resp_empty);
prgen_fifo #(2+4, 4)
resp_fifo(
.clk(clk),
.reset(reset),
.push(resp_push),
.pop(resp_pop),
.din({cmd_resp,
WID
}
),
.dout({BRESP,
BID
}
),
.empty(resp_empty),
.full(resp_full)
);
endmodule
//------------------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- RobustVerilog version 1.5g (limited free version) Jul 5 2011
//-- Invoked Sun Oct 09 23:51:01 2011
//-- Source file: axi2ahb_rd_fifo.v
//-- Parent file: axi2ahb.v
//-- Project directory: D:/axi2ahb/robust_axi2ahb/trunk/run/
//-- Target directory: out/
//-- Command flags: ..\..\..\..\robust.exe ../robust_reg.pro -gui
//-- www.provartec.com/edatools ... info@provartec.com
//------------------------------------------------------------------
module axi2ahb_rd_fifo (clk,reset,RID,RDATA,RRESP,RLAST,RVALID,RREADY,HRDATA,HREADY,HTRANS,HRESP,cmd_id,cmd_err,rdata_phase,rdata_ready,data_last);
parameter FIFO_LINES = 32; //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
input clk;
input reset;
output [3:0] RID;
output [31:0] RDATA;
output [1:0] RRESP;
output RLAST;
output RVALID;
input RREADY;
input [32-1:0] HRDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input [4-1:0] cmd_id;
input cmd_err;
input rdata_phase;
output rdata_ready;
input data_last;
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
reg RVALID;
reg [2:0] burst_cnt;
wire axi_last;
wire ahb_last;
wire [1:0] cmd_resp;
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
assign rdata_ready = burst_cnt < 'd2;
assign data_push = rdata_phase & HREADY;
assign data_pop = RVALID & RREADY;
assign axi_last = RVALID & RREADY & RLAST;
assign ahb_last = rdata_phase & data_last;
always @(posedge clk or posedge reset)
if (reset)
burst_cnt <= #1 'd0;
else if (axi_last | ahb_last)
burst_cnt <= #1 burst_cnt - axi_last + ahb_last;
prgen_fifo #(32+4+2+1, FIFO_LINES)
data_fifo(
.clk(clk),
.reset(reset),
.push(data_push),
.pop(data_pop),
.din({HRDATA,
cmd_id,
cmd_resp,
ahb_last
}
),
.dout({RDATA,
RID,
RRESP,
RLAST
}
),
.empty(data_empty),
.full(data_full)
);
always @(posedge clk or posedge reset)
if (reset)
RVALID <= #1 1'b0;
else if (axi_last)
RVALID <= #1 1'b0;
else if (burst_cnt > 'd0)
RVALID <= #1 1'b1;
else
RVALID <= #1 1'b0;
endmodule[/url] |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2011-10-31 00:13:50
