Assisted Phase-Lock Acquistion Method For Integer-N Charge-Pump PLL

hi_china59 · 发表于 2011-10-17 14:08:22

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Assisted Phase-Lock Acquistion Method For Integer-N Charge-Pump Phase-Lock Loops
TABLE OF CONTENTS
LIST OF FIGURES.............................................iii
LIST OF TABLES................................................ v
ACKNOWLEDGMENTS .................................... vi
Chapter 1 Introduction................................... 1
1.1 Motivation............................................... 1
1.2 Thesis Outline .......................................... 2
Chapter 2 Receiver and Transmitter Architectures for Bluetooth ................................................. 4
2.1 Receiver Architectures............................. 4
2.1.1 High IF Architecture......................... 4
2.1.2 Low IF Architecture ......................... 6
2.1.3 Very Low IF Architecture................. 7
2.1.4 Direct Conversion Architecture......... 8
2.2 Transmitter Architectures....................... 9
2.2.1 Fractional-N Architecture ................. 9
2.2.2 Dual Port Architecture .................... 10
2.2.3 Open Loop Architecture.................. 11
2.3 K-State Bluetooth Transceiver .............. 12
2.3.1 Receiver ......................................... 13
2.3.2 Transmitter ..................................... 15
2.3.3 Solutions of Low-Sensitivity VCO Problems.................................................................... 15
Chapter 3 Integer-N Charge-Pump Phase-Locked Loops.............................................................. 17
3.1 Type-II, Second Order, Charge-Pump PLL........................................................................... 18
3.1.1 Phase-Frequency Detector and Charge-Pump ................................................................... 18
3.1.2 Loop Filter, Voltage Controlled Oscillator and Loop Transfer Function............................ 20
3.1.3 Loop Bandwidth ............................. 22
3.2 Type-II, Third Order Charge-Pump PLL.............................................................................. 23
3.2.1 Designing PLLs for Loop Bandwidth and Phase Margin................................................... 23
Chapter 4 Loop Dynamics and Charge-Pump Saturation ............................................................. 28
4.1 Loop Dynamics During Acquisition ...... 28
4.2 Charge-Pump Saturation....................... 30
4.3 PLL Design Example ............................. 32
Chapter 5 Assisted Phase-Lock Acquisition Method ..................................................................... 37
CONFIDENTIAL: Pending invention disclosure.
Chapter 6 Conclusions and Future Work ..... 45
6.1 Conclusions ............................................ 45
6.2 Future Work .......................................... 47
References........................................................... 48
Appendix A: Block Diagram of the KSU6989 Bluetooth ransceiver................................................. 51
Appendix B: Details of the Derivation of Equation .28..................................................................... 52
Appendix C: Frequency Synthesizer Circuit Design ....................................................................... 54