模块化串口设计问题

517650971 · 发表于 2011-10-17 11:43:27

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

我是要设计一个通过串口来控制一个五位的LED灯，但是串口数据发过去后LED无反应
module led(clk,rst_n,rs232_rx,LED,LED_com);

input clk;
input rst_n;
input rs232_rx;
output[5:0] LED;
output LED_com;

wire bps_start;
wire clk_bps;
wire[7:0] rx_data;
wire rx_int;
//---------------------------------

led_bps bps(
   .clk(clk),
   .rst_n(rst_n),
   .bps_start(bps_start),
   .clk_bps(clk_bps)
   );

//---------------------------------

led_rx rx(
   .clk(clk),
   .rst_n(rst_n),
   .rs232_rx(rs232_rx),
   .clk_bps(clk_bps),
   .bps_start(bps_start),
   .rx_data(rx_data),
   .rx_int(rx_int)
   );

//---------------------------------

led_key key(
   .clk(clk),
   .rst_n(rst_n),
   .LED(LED),
   .LED_com(LED_com)
   );

//---------------------------------
endmodule

517650971 · 发表于 2011-10-17 11:46:03

module led_bps(clk,rst_n,bps_start,clk_bps);

input clk;
input rst_n;
input bps_start; //接受数据后波特率时钟启动信号
output clk_bps; //clk_bpa的高电平为接受或者发送数据位中间采样点

/*
paramter hps9600 = 5207, //波特率9600bps
hps19200 = 2603, //波特率19200bps
hps38400 = 1301, //波特率38400bps
hps57600 = 867, //波特率57600bps
hps115200 = 433; //波特率115200bps

paramter bps9600_2 =2603,
bps19200_2 =1301,
bps38400_2 =867,
bps57600_2 =433,
bps115200_2 =216;
*/

`define BPS_PARA 5207 //波特率为9600时的分频计数值
`define BPS_PARA_2 2603 //波特率为9600时的分频计数值的一半，用于数据采样
//-------------------------------

reg[12:0] cnt;

always @(posedge clk or negedge rst_n)
if(!rst_n) cnt<=13'd0;
else if(cnt==`BPS_PARA) cnt<=13'd0;
else if(bps_start) cnt<=cnt+1'd1;

reg clk_bps_r;

always @(posedge clk or negedge rst_n)
if(!rst_n) clk_bps_r<=1'd0;
else if(cnt==`BPS_PARA_2) clk_bps_r<=1'b1;
else clk_bps_r<=1'b0;

assign clk_bps=clk_bps_r;

endmodule

517650971 · 发表于 2011-10-17 11:47:22

`timescale 1ns / 1ps
module led_rx(clk,rst_n,rs232_rx,clk_bps,bps_start,rx_data,rx_int);

input clk;
input rst_n;
input rs232_rx;
input clk_bps;
output bps_start;
output[7:0] rx_data;
output rx_int;

//-----------------------------------

reg rs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;
wire neg_rs232_rx;

always @(posedge clk or negedge rst_n)
if(!rst_n) begin
rs232_rx0<=1'b0;
rs232_rx1<=1'b0;
rs232_rx2<=1'b0;
rs232_rx3<=1'b0;
end
else begin
rs232_rx0<=rs232_rx;
rs232_rx1<=rs232_rx0;
rs232_rx2<=rs232_rx1;
rs232_rx3<=rs232_rx2;
end

assign neg_rs232_rx= rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0;

//-----------------------------------

reg bps_start_r;
reg[3:0] num; //移位次数
reg rx_int; //接收中断信号,接收数据期间为高电平

always @(posedge clk or negedge rst_n)
if(!rst_n) begin
bps_start_r<=1'b0;
rx_int<=1'b0;
end
else if(neg_rs232_rx) begin
bps_start_r<=1'b1;
rx_int<=1'b1;
end
else if(num==4'd12) begin
bps_start_r<=1'b0;
rx_int<=1'b0;
end

assign bps_start=bps_start_r;

//-----------------------------------

reg[7:0] rx_data_r; //串口接收数据寄存器，保存直至下一个数据来到
reg[7:0] rx_temp_data; //接收数据寄存器

always @(posedge clk or negedge rst_n)
if(!rst_n) begin
rx_data_r<=8'd0;
rx_temp_data<=8'd0;
num<=4'd0;
end
else if(rx_int) begin
if(clk_bps) begin
num<=num+1'b1;
case(num)
4'd1: rx_temp_data[0] <= rs232_rx; //锁存第0bit
4'd2: rx_temp_data[1] <= rs232_rx; //锁存第1bit
4'd3: rx_temp_data[2] <= rs232_rx; //锁存第2bit
4'd4: rx_temp_data[3] <= rs232_rx; //锁存第3bit
4'd5: rx_temp_data[4] <= rs232_rx; //锁存第4bit
4'd6: rx_temp_data[5] <= rs232_rx; //锁存第5bit
4'd7: rx_temp_data[6] <= rs232_rx; //锁存第6bit
4'd8: rx_temp_data[7] <= rs232_rx; //锁存第7bit
default: ;
endcase
end
else if(num==4'd12) begin
rx_data_r<=rx_temp_data;
num<=4'd0;
end
end

//-----------------------------------

assign rx_data=rx_data_r;

endmodule

517650971 · 发表于 2011-10-17 11:48:49

`timescale 1ns / 1ps
module led_key(clk,rst_n,LED[5:0],LED_com,rx_temp_data);

input clk;
input rst_n;
output[5:0] LED;
output LED_com;
output[7:0] rx_temp_data;
//---------------------------------

reg[24:0] cnt;

always @(posedge clk or negedge rst_n)
if(!rst_n) cnt<=25'd0;
else if(cnt==25'h1FFFFFF) cnt<=25'd0;
else cnt<=cnt+1'd1;

//---------------------------------

reg[5:0] LED_r;

always @(posedge clk or negedge rst_n)
if(!rst_n) LED_r<=6'd0;
// if(!rst_n) LED_r<=6'b111110;
else if(cnt==25'h1FFFFFF) LED_r<={rx_temp_data[0],rx_temp_data[1],rx_temp_data[2],rx_temp_data[3],rx_temp_data[4],rx_temp_data[5]};
//LED_r<={LED_r[0],LED_r[5],LED_r[4],LED_r[3],LED_r[2],LED_r[1]};

//---------------------------------

assign LED=LED_r;
assign LED_com=1'd1;

endmodule

517650971 · 发表于 2011-10-17 11:49:54

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Mon Oct 17 11:26:45 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file led_rx.v
Info: Found entity 1: led_rx
Info: Found 1 design units, including 1 entities, in source file led_bps.v
Info: Found entity 1: led_bps
Info: Found 1 design units, including 1 entities, in source file led_key.v
Info: Found entity 1: led_key
Warning: Using design file led.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: led
Info: Elaborating entity "led" for the top level hierarchy
Info: Elaborating entity "led_bps" for hierarchy "led_bps:bps"
Info: Elaborating entity "led_rx" for hierarchy "led_rx:rx"
Info: Elaborating entity "led_key" for hierarchy "led_key:key"
Warning (10030): Net "rx_temp_data[5..0]" at led_key.v(8) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "rx_temp_data[7..6]" at led_key.v(8) has no driver
Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "LED[0]" is stuck at GND
Warning (13410): Pin "LED[1]" is stuck at GND
Warning (13410): Pin "LED[2]" is stuck at GND
Warning (13410): Pin "LED[3]" is stuck at GND
Warning (13410): Pin "LED[4]" is stuck at GND
Warning (13410): Pin "LED[5]" is stuck at GND
Warning (13410): Pin "LED_com" is stuck at VCC
Info: 25 registers lost all their fanouts during netlist optimizations. The first 25 are displayed below.
Info: Register "led_key:key|cnt[24]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[23]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[22]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[21]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[20]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[19]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[18]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[17]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[16]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[15]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[14]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[13]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[12]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[11]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[10]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[9]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[8]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[7]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[6]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[5]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[4]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[3]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[2]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[1]" lost all its fanouts during netlist optimizations.
Info: Register "led_key:key|cnt[0]" lost all its fanouts during netlist optimizations.
Info: Generating hard_block partition "hard_block:auto_generated_inst"
Warning: Design contains 3 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
Warning (15610): No output dependent on input pin "rst_n"
Warning (15610): No output dependent on input pin "rs232_rx"
Info: Implemented 10 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 7 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
Info: Peak virtual memory: 248 megabytes
Info: Processing ended: Mon Oct 17 11:26:46 2011
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Mon Oct 17 11:26:47 2011
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led -c led
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EP1C12Q240C8 for design "led"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP1C6Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
Info: Pin ~nCSO~ is reserved at location 24
Info: Pin ~ASDO~ is reserved at location 37
Info: Timing-driven compilation is using the TimeQuest Timing Analyzer
Critical Warning: Synopsys Design Constraints File file not found: 'led.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Router estimated average interconnect usage is 0% of the available device resources
Info: Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Generated suppressed messages file E:/FPGA/kaifaban/chuankou/kongzhiLED/led.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 321 megabytes
Info: Processing ended: Mon Oct 17 11:26:50 2011
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Mon Oct 17 11:26:51 2011
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off led -c led
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Mon Oct 17 11:26:51 2011
Info: Command: quartus_sta led -c led
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Assembler is generating device programming files
Critical Warning: Synopsys Design Constraints File file not found: 'led.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: No clocks to report
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: No Minimum Pulse Width paths to report
Info: The selected device family is not supported by the report_metastability command.
Info: Design is fully constrained for setup requirements
Info: Design is fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 222 megabytes
Info: Processing ended: Mon Oct 17 11:26:52 2011
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 247 megabytes
Info: Processing ended: Mon Oct 17 11:26:52 2011
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Mon Oct 17 11:26:54 2011
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off led -c led
Info: Generated simulation netlist will be non-hierarchical because the design has SignalTap II partitions, termination control logic and/or a design partition that contains bidirectional ports
Info: Generated files "led.vo" and "led_v.sdo" in directory "E:/FPGA/kaifaban/chuankou/kongzhiLED/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 218 megabytes
Info: Processing ended: Mon Oct 17 11:26:54 2011
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: Quartus II Full Compilation was successful. 0 errors, 21 warnings

solarwafer · 发表于 2011-10-17 13:06:49

还是问些具体一点的东西吧，看代码估计没人愿意详细的看，因为特别花时间

zhuyuan0827 · 发表于 2011-10-17 16:53:58

rx_data,rx_int,rx_temp_data???

孑然儿 · 发表于 2011-11-24 10:18:26

警告不用管，可能是设计逻辑的问题。另外用好Quartus的help很有帮助

个儒 · 发表于 2014-5-15 10:28:03

太乱了，自己先梳理一遍，不懂的再调出来问

[求助] 模块化串口设计问题

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

相关帖子

站长推荐 /2