always @(posedge clk_32k or negedge rstn) begin
if(!rstn)
en1_32k <= 1'b0;
else if(set_en_32k)
en1_32k <= 1'b1;
else if(clr_en_32k)
en1_32k <= 1'b0;
end
always @(posedge clk_1M or negedge rstn) begin
if(!rstn) begin
en1 <= 1'b0;
en1_1M_d2 <= 1'b0;
en1_1M_d1 <= 1'b0;
end
else begin
en1 <= en1_1M_d2;
en1_1M_d2 <= en1_1M_d1;
en1_1M_d1 <= en1_32k;
end
end