Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design

angelweishan

JOURNAL OF COMPUTERS, VOL. 3, NO. 4, APRIL 2008
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design

Abstract—The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer life-time of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18μm epi-digital CMOS technology for ZigBee applications, which consumed 7.95mW from 1.8V supply. The synthesizer has achieved phase-noise of −81.55dBc/Hz and −108.55dBc/Hz at 100kHz and 1MHz offset, respectively. The settling time measured is less than 25μs for an output frequency change of 75MHz from 2.4GHz. The chip core area is 0.75 × 0.65mm2. Index Terms—Frequency  ynthesizers, phase locked loops (PLLs), oscillators, integer-N topology, ZigBee standards, system-on-chip solution, low-power design.

chujn

下来看看，谢谢。

jamesccp

板凳！！！谢谢楼主。

fwutsairlin

THANK YOU

reptilian77

Thanks. Interesting

Eidahmed26

Thanks

jingxin_xd

谢谢楼主。