紧急在线求助，一个verilog综合问题

taoying · 发表于 2011-10-7 20:54:33

我是一个初学者，下面是我写的一个异步fifo，忘高手不要见笑，呵呵

module fifo(clka,clkb,rd_en,wt_en,full,empty,clr,din,dout);

parameter width = 7,
 addr_width = 9,
 max_width = 1023,
 gray_txt = 10'b1000000000;

input clka,clkb,clr,rd_en,wt_en;
input[width:0] din;
output[width:0] dout;
output full,empty;

reg[width:0] dout;
reg full,empty;
reg[width:0] remb[0:max_width];
reg[addr_width:0] rd_p,wt_p;
reg txta,txtb;

// write data
always @(posedge clka)
begin
if(full == 0 && wt_en)
remb[wt_p] <= din;
end

// read data
always @(posedge clkb)
begin
if(empty == 0 && rd_en)
dout <= remb[rd_p];
end

//write pointer
always @(posedge clka or negedge clr)
begin
wt_p <= gray(clr,(full || wt_en == 0));
end

//read pointer
always @(posedge clkb or negedge clr)
begin
rd_p <= gray1(clr,(empty || rd_en == 0));
end

//singal txta for write
always @(posedge clka or negedge clr)
begin
if(!clr)
txta <= 0;
else if(wt_p == gray_txt)
txta <= ~txta;
end

//singal txtb for read
always @(posedge clkb or negedge clr)
begin
if(!clr)
txtb <= 0;
else if(rd_p == gray_txt)
txtb <= ~txtb;
end

// full generate
always @(posedge clka or negedge clr)
begin
if(!clr)
full <= 0;
else if(txta == ~txtb && wt_p == rd_p)
full <= 1;
else
full <= 0;
end

// empty generate
always @(posedge clkb or negedge clr)
begin
if(!clr)
empty <= 1;
else if(txta == txtb && wt_p == rd_p)
empty <= 1;
else
empty <= 0;
end

//gray for address pointer
function[addr_width:0] gray;
input clr;
input en;

reg[addr_width:0] cnt;

begin
cnt = clr? (en ? cnt : (cnt + 1)) : 0;
/*
if(clr)
begin
 if(en)
 cnt = cnt;
 else
 cnt = cnt + 1;
end
 else
cnt = 0;
*/

gray[addr_width] = 0 ^ cnt[addr_width];
gray[addr_width - 1] = cnt[addr_width] ^ cnt[addr_width - 1];
gray[addr_width - 2] = cnt[addr_width - 1] ^ cnt[addr_width - 2];
gray[addr_width - 3] = cnt[addr_width - 2] ^ cnt[addr_width - 3];
gray[addr_width - 4] = cnt[addr_width - 3] ^ cnt[addr_width - 4];
gray[addr_width - 5] = cnt[addr_width - 4] ^ cnt[addr_width - 5];
gray[addr_width - 6] = cnt[addr_width - 5] ^ cnt[addr_width - 6];
gray[addr_width - 7] = cnt[addr_width - 6] ^ cnt[addr_width - 7];
gray[addr_width - 8] = cnt[addr_width - 7] ^ cnt[addr_width - 8];
gray[addr_width - 9] = cnt[addr_width - 8] ^ cnt[addr_width - 9];

end
endfunction

function[addr_width:0] gray1;
input clr;
input en;

reg[addr_width:0] cnt;

begin
cnt = clr? (en ? cnt : (cnt + 1)) : 0;
/*
if(clr)
begin
 if(en)
 cnt = cnt;
 else
 cnt = cnt + 1;
end
 else
cnt = 0;
*/

gray1[addr_width] = 0 ^ cnt[addr_width];
gray1[addr_width - 1] = cnt[addr_width] ^ cnt[addr_width - 1];
gray1[addr_width - 2] = cnt[addr_width - 1] ^ cnt[addr_width - 2];
gray1[addr_width - 3] = cnt[addr_width - 2] ^ cnt[addr_width - 3];
gray1[addr_width - 4] = cnt[addr_width - 3] ^ cnt[addr_width - 4];
gray1[addr_width - 5] = cnt[addr_width - 4] ^ cnt[addr_width - 5];
gray1[addr_width - 6] = cnt[addr_width - 5] ^ cnt[addr_width - 6];
gray1[addr_width - 7] = cnt[addr_width - 6] ^ cnt[addr_width - 7];
gray1[addr_width - 8] = cnt[addr_width - 7] ^ cnt[addr_width - 8];
gray1[addr_width - 9] = cnt[addr_width - 8] ^ cnt[addr_width - 9];

end
endfunction

endmodule

我用synplify综合，综合结果如下：

Implementation: fifo

#Fri Oct 07 20:28:46 2011

<a name=compilerReport56>$ Start of Compile</a>
#Fri Oct 07 20:28:46 2011

Synplicity Verilog Compiler, version 1.0, Build 037R, built Oct 30 2008
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved

@I::"F:\worksoft\synplicity\fpga_962\lib\xilinx\unisim.v"
@I::"E:\sim_test\synplify\fifo\fifo.v"
Verilog syntax check successful!
File E:\sim_test\synplify\fifo\fifo.v changed - recompiling
Selecting top level module fifo
@N:<a href="@N:CG364

XP_HELP">CG364</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:1:7:1:11

N:CG364

XP_MSG">fifo.v(1)</a><!@TM:1317990527> | Synthesizing module fifo

@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:21:1:21:7:@N:CL134:@XP_MSG">fifo.v(21)</a><!@TM:1317990527> | Found RAM remb, depth=1024, width=8
@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <9> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <8> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <7> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <6> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <5> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <4> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <3> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <2> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL171:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register bit <1> of rd_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <9> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <8> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <7> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <6> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <5> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <4> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <3> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <2> of wt_p[9:0] 

@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL171:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register bit <1> of wt_p[9:0] 

@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL189:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Register bit wt_p[0] is always 0, optimizing ...
@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL189:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Register bit rd_p[0] is always 0, optimizing ...
@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:35:1:35:7:@W:CL169:@XP_MSG">fifo.v(35)</a><!@TM:1317990527> | Pruning Register wt_p[0] 

@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:41:1:41:7:@W:CL169:@XP_MSG">fifo.v(41)</a><!@TM:1317990527> | Pruning Register rd_p[0] 

@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:76:1:76:7:@W:CL190:@XP_MSG">fifo.v(76)</a><!@TM:1317990527> | Optimizing register bit empty to a constant 1
@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:65:1:65:7:@W:CL190:@XP_MSG">fifo.v(65)</a><!@TM:1317990527> | Optimizing register bit full to a constant 0
@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:65:1:65:7:@W:CL169:@XP_MSG">fifo.v(65)</a><!@TM:1317990527> | Pruning Register full 

@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:76:1:76:7:@W:CL169:@XP_MSG">fifo.v(76)</a><!@TM:1317990527> | Pruning Register empty 

@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:21:1:21:7:@W:CL169:@XP_MSG">fifo.v(21)</a><!@TM:1317990527> | Pruning Register remb[7:0] 

@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:8:7:8:11:@W:CL159:@XP_MSG">fifo.v(8)</a><!@TM:1317990527> | Input clka is unused
@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:8:21:8:26:@W:CL159:@XP_MSG">fifo.v(8)</a><!@TM:1317990527> | Input rd_en is unused
@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:8:27:8:32:@W:CL159:@XP_MSG">fifo.v(8)</a><!@TM:1317990527> | Input wt_en is unused
@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:8:17:8:20:@W:CL159:@XP_MSG">fifo.v(8)</a><!@TM:1317990527> | Input clr is unused
@W:<a href="@W:CL159:@XP_HELP">CL159</a> : <a href="E:\sim_test\synplify\fifo\fifo.v:9:16:9:19:@W:CL159:@XP_MSG">fifo.v(9)</a><!@TM:1317990527> | Input din is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Oct 07 20:28:47 2011

###########################################################]
<a name=mapperReport57>Synplicity Xilinx Technology Mapper, Version 9.6, Build 033R, Built Oct 30 2008 18:01:10</a>
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
Product Version Version 9.6.2
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1317990528> | Running in 32-bit mode.
@N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1317990528> | Gated clock conversion enabled
Reading Xilinx I/O pad type table from file [F:\worksoft\synplicity\fpga_962\lib\xilinx\x_io_tbl.txt]
Reading Xilinx Rocket I/O parameter type table from file [F:\worksoft\synplicity\fpga_962\lib\xilinx\gttype.txt]

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N:<a href="@N:BN116:@XP_HELP">BN116</a> : <a href="e:\sim_test\synplify\fifo\fifo.v:28:1:28:7:@N:BN116:@XP_MSG">fifo.v(28)</a><!@TM:1317990528> | Removing sequential instance dout[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[

================================================================
Instance

in Generated Clock Optimization Status
================================================================

######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.fifo(verilog):
No nets needed buffering.

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1317990528> | The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Writing Analyst data base E:\sim_test\synplify\fifo\fifo\fifo.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1317990528> | Writing default property annotation file E:\sim_test\synplify\fifo\fifo\fifo.map.
Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file [F:\worksoft\synplicity\fpga_962\lib\xilinx\netattr.txt]
Version 9.6.2
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

@N:<a href="@N:MF276:@XP_HELP">MF276</a> : <!@TM:1317990528> | Gated clock conversion enabled, but no gated clocks found in design
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

@N:<a href="@N:MF333:@XP_HELP">MF333</a> : <!@TM:1317990528> | Generated clock conversion enabled, but no generated clocks found in design
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Found clock fifo|clkb with period 25.00ns

<a name=timingReport58>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Fri Oct 07 20:28:48 2011
#

Top view: fifo
Requested Frequency: 40.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1317990528> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1317990528> | Clock constraints cover only FF-to-FF paths associated with the clock..

<a name=performanceSummary59>

erformance Summary </a>
*******************

Worst slack in design: NA

<a name=clockRelationships60>Clock Relationships</a>
*******************

Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

<a name=interfaceInfo61>Interface Information </a>
*********************

No IO constraint found

##### END OF TIMING REPORT #####]

---------------------------------------
<a name=resourceUsage62>Resource Usage Report for fifo </a>

Mapping to part: xc2v1000bg575-6
Cell usage:
GND 1 use
VCC 1 use

I/O ports: 23
I/O primitives: 10
OBUF 10 uses

I/O Register bits: 0
Register bits not including I/Os: 0 (0%)
Total load per clock:

Mapping Summary:
Total LUTs: 0 (0%)

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Oct 07 20:28:48 2011

###########################################################]

结果我发现RTL视图只有一个触发器，其他什么都没有。technology图形也只有一些buffer
我怀疑是verilog没有描述好，但是我也找不出哪里错了，忘高手指教

在线等待·······

chlor · 发表于 2011-10-7 20:54:34

function描述有问题，function需是组合逻辑才可综合，但你里面的cnt是什么？可以改一种描述方式，把cnt拿到function外面来。
另外，你的部分always语句敏感列表中有negedge clr，但是没有对应的if(!clr)分支。

taoying · 发表于 2011-10-8 19:44:51

回复 2# chlor

多谢提醒，最后修改了，好了

[讨论] 紧急在线求助，一个verilog综合问题

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